M55D1G1664A-EEBIG2Y
| Part Description |
LPDDR3 SDRAM 1Gb (64Mbx16) 933MHz 1.8V/1.2V 178-BGA Industrial Grade, Pb-free |
|---|---|
| Quantity | 985 Available (as of May 5, 2026) |
Specifications & Environmental
| Device Package | 178-BGA (10x11.5) | Memory Format | DRAM | Technology | DRAM | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 1 Gbit | Access Time | 5.5 ns | Grade | Industrial | ||
| Clock Frequency | 933 MHz | Voltage | 1.14V ~ 1.30V, 1.70V ~ 1.95V | Memory Type | Volatile | ||
| Operating Temperature | -40°C – 85°C | Write Cycle Time Word Page | 15 ns | Packaging | 178-BGA | ||
| Mounting Method | Surface Mount | Memory Interface | Parallel | Memory Organization | 64M x 16 | ||
| Moisture Sensitivity Level | 3 | RoHS Compliance | Compliant | REACH Compliance | REACH Unknown | ||
| Qualification | JEDEC | ECCN | EAR99 | HTS Code | 8542.32.00.32 |
Overview of M55D1G1664A-EEBIG2Y – LPDDR3 SDRAM 1Gb (64Mbx16) 933MHz 1.8V/1.2V 178-BGA Industrial Grade, Pb-free
The M55D1G1664A-EEBIG2Y is a 1.074 Gbit LPDDR3 SDRAM organized as 64M × 16 with eight internal banks and JEDEC LPDDR3 compliance. It delivers double-data-rate operation at a maximum clock frequency of 933 MHz (1866 Mb/s per pin data rate) with support for industrial temperature operation from −40 °C to 85 °C.
Designed for industrial-grade memory subsystems, this device offers low-voltage core and I/O operation, advanced DDR features for timing calibration, and a compact 178-ball BGA package for surface-mount integration.
Key Features
- Memory Organization — 1.074 Gbit capacity arranged as 64M × 16 with 8 banks and a 4KB page size, supporting high-density memory mapping for embedded systems.
- Performance — Operates up to 933 MHz clock frequency (1866 Mb/s per pin) with selectable read latencies (RL options include 3, 6, 8, 9, 10, 11, 12, 14, 16) and a burst length of 8 for sustained data throughput.
- Low-Voltage Power Domains — Separate supply domains: VDD1 = 1.70–1.95 V and VDD2 / VDDCA / VDDQ = 1.14–1.30 V, enabling lower-power operation for core and I/O.
- DDR Architecture & I/O — Eight-bit prefetch DDR architecture, bidirectional/differential per-byte DQS strobes, differential clock inputs (CK_t/CK_c), and data mask (DM) support for reliable high-speed transfers.
- Timing and Training — Supports CA training and write leveling for clock-to-DQ, DQS and DM timing adjustment, improving interface margin in system designs.
- Advanced Power & Refresh — Per-bank refresh, auto temperature compensated self refresh (ATCSR), partial-array self refresh (PASR), deep power-down (DPD), and standard auto/self refresh modes for flexible power management.
- System Controls — Programmable drive strength (DS), on-die termination (ODT), bank masking, and segment masking for optimized signal integrity and power/performance trade-offs.
- Package & Mounting — Pb-free 178-ball BGA (10 × 11.5 mm) surface-mount package suitable for compact board-level integration in industrial designs.
Typical Applications
- Industrial Systems — Provides JEDEC LPDDR3 memory in designs that require operation across −40 °C to 85 °C and robust refresh/power management features.
- Embedded Memory Subsystems — Suitable for controllers and modules that need a 1Gb LPDDR3 device with per-bank refresh and advanced power states like deep power-down and self-refresh.
- High-Speed Interfaces — Useful where differential clocks, per-byte DQS, and write leveling/CA training are required to maintain timing margin at high data rates.
Unique Advantages
- Industrial Temperature Range — Guaranteed operation from −40 °C to 85 °C for deployment in temperature-challenging environments.
- Low-Voltage Dual Supply — Separate core and I/O voltage ranges (VDD1 and VDD2/VDDCA/VDDQ) enable optimized power distribution and reduced power consumption.
- JEDEC LPDDR3 Compliance — Conforms to LPDDR3 standards with features such as eight internal banks, BL8 bursts, and standard refresh mechanisms for predictable system behavior.
- High Data Rate Capability — 933 MHz clocking (1866 Mb/s per pin data rate) with flexible read-latency options to match system timing requirements.
- Comprehensive Power Management — ATCSR, PASR, DPD and per-bank refresh modes provide designers with multiple strategies to balance power vs. availability.
- Compact, Pb-free BGA — 178-ball BGA (10 × 11.5 mm) package offers high density and Pb-free compliance for modern assembly processes.
Why Choose M55D1G1664A-EEBIG2Y?
The M55D1G1664A-EEBIG2Y positions itself as a JEDEC-compliant LPDDR3 memory device that combines high data-rate operation, flexible voltage domains, and industrial-grade temperature capability. Its feature set—including CA training, write leveling, per-bank refresh, and deep power-down—supports reliable integration into industrial and embedded memory subsystems.
Backed by ESMT’s LPDDR3 design and provided in a compact 178-BGA Pb-free package, this part is suited for designs that require predictable timing, robust power-management options, and operation across wide temperature ranges.
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Date Founded: 1998
Headquarters: Hsinchu Science Park, Hsinchu, Taiwan
Employees: 400+
Revenue: $377.8 Million
Certifications and Memberships: N/A