MT46V32M8TG-75 IT:G TR
| Part Description |
IC DRAM 256MBIT PARALLEL 66TSOP |
|---|---|
| Quantity | 236 Available (as of May 5, 2026) |
| Product Category | Memory |
|---|---|
| Manufacturer | Micron Technology Inc. |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 66-TSOP | Memory Format | DRAM | Technology | SDRAM - DDR | ||
|---|---|---|---|---|---|---|---|
| Memory Size | 256 Mbit | Access Time | 750 ps | Grade | Industrial | ||
| Clock Frequency | 133 MHz | Voltage | 2.3V ~ 2.7V | Memory Type | Volatile | ||
| Operating Temperature | -40°C ~ 85°C (TA) | Write Cycle Time Word Page | 15 ns | Packaging | 66-TSSOP (0.400", 10.16mm Width) | ||
| Mounting Method | Volatile | Memory Interface | Parallel | Memory Organization | 32M x 8 | ||
| Moisture Sensitivity Level | 2 (1 Year) | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Qualification | N/A | ECCN | EAR99 | HTS Code | 8542.32.0024 |
Overview of MT46V32M8TG-75 IT:G TR – IC DRAM 256Mbit Parallel 66-TSSOP
The MT46V32M8TG-75 IT:G TR is a 256 Mbit DDR SDRAM organized as 32M × 8 with a parallel memory interface in a 66-pin TSSOP package. It implements a double-data-rate internal pipelined architecture with source-synchronous data capture (DQS) to support two data transfers per clock cycle.
Targeted for systems requiring mid-density DDR memory in a compact footprint, this device delivers 133 MHz clock operation, industrial temperature range, programmable burst lengths, and SSTL_2-compatible 2.5V I/O for board-level memory expansion in embedded and industrial applications.
Key Features
- Core / Architecture Double Data Rate (DDR) SDRAM with internal pipelined DDR architecture enabling two data accesses per clock cycle; includes DLL for DQ/DQS alignment and differential clock inputs (CK, CK#).
- Memory Organization 256 Mbit capacity organized as 32M × 8 with four internal banks for concurrent operation.
- Performance Supports 133 MHz clock frequency (speed grade -75), 750 ps access time, and a 15 ns write cycle time (word page).
- Data I/O and Timing Source-synchronous DQS (edge-aligned for READs, center-aligned for WRITEs), programmable burst lengths of 2, 4, or 8, and data mask (DM) functionality.
- Power Operates from a 2.3 V to 2.7 V supply (VDD/VDDQ nominal 2.5 V), with 2.5 V I/O compatible with SSTL_2 signaling.
- Reliability and Refresh Auto refresh and 8K refresh-cycle support; self-refresh option noted in datasheet options.
- Package and Temperature 66-TSSOP package (0.400" / 10.16 mm width) and industrial operating temperature range of –40°C to +85°C (TA).
Typical Applications
- Industrial Embedded Systems Provides mid-density DDR memory for controllers and processing modules that require operation across –40°C to +85°C.
- Board-Level Memory Expansion Compact 66-TSSOP footprint and 2.5 V SSTL_2-compatible I/O enable integration as on-board DRAM for legacy parallel DDR designs.
- Memory for Source-Synchronous Designs DQS-based source-synchronous data capture supports systems that require precise timing between data and strobe signals.
Unique Advantages
- Mid-density DDR in a compact package: 256 Mbit capacity in a 66-TSSOP (10.16 mm width) package minimizes board area for additional system memory.
- Industrial temperature rating: Specified for –40°C to +85°C (TA) for deployment in temperature-demanding embedded applications.
- Source-synchronous data capture (DQS): DQS transmitted/received with data improves timing margins for read and write operations.
- Flexible timing and burst options: Programmable burst lengths (2, 4, 8) and multiple timing grades give designers trade-offs between latency and throughput.
- SSTL_2-compatible I/O and standard DDR signaling: 2.5 V I/O and differential clock inputs (CK/CK#) align with common DDR board-level interfaces.
Why Choose MT46V32M8TG-75 IT:G TR?
The MT46V32M8TG-75 IT:G TR combines DDR performance, practical capacity, and an industrial temperature rating in a compact 66-TSSOP package. Its source-synchronous DQS, programmable burst lengths, and 2.5 V SSTL_2-compatible I/O provide the timing flexibility and interface compatibility needed for embedded and industrial DDR memory applications.
This device is suited to designers seeking a reliable mid-density DDR SDRAM solution for board-level memory expansion or legacy parallel DDR architectures where compact footprint, industrial temperature range, and controlled timing characteristics are required. Multiple timing options and industry-standard DDR features support integration into systems with defined latency and throughput requirements.
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