LX2160XC72029B

IC MPU QORLQ LX2 2GHZ 1517FCPBGA
Part Description

ARM® Cortex®-A72 Microprocessor IC QorlQ LX2 16 Core, 64-Bit 2GHz 1517-FCPBGA (40x40)

Quantity 1,251 Available (as of October 8, 2026)
Product CategoryMicroprocessors
Part SeriesLX2160X
ManufacturerNXP USA Inc.
Manufacturing StatusActive
Manufacturer Standard Lead Time18 Weeks
Datasheet

Specifications & Environmental

Core ProcessorARM® Cortex®-A72Device Package1517-FCPBGA (40x40)ECCN5A002A1 NXP
Ethernet100Gbps (2)Graphics AccelerationYesHTS Code8542.31.0001
Moisture Sensitivity Level3 (168 Hours)Mounting MethodSurface MountMounting TypeSurface Mount
Number of Cores/Bus Width16 Core, 64-BitOperating Temperature-40°C ~ 105°C (TJ)Package / Case1517-BBGA, FCBGA
RAM ControllersDDR4REACH ComplianceREACH UnaffectedRoHS ComplianceROHS3 Compliant
SATASATA 3.0 (4)Security FeaturesSecure Boot, TrustZone®Speed2GHz
Supplier Device Package1517-FCPBGA (40×40)USBUSB 3.0 (2) + PHY (2)Voltage – I/O1.2V, 1.8V, 3.3V

Overview of LX2160XC72029B – IC MPU QORLQ LX2 2GHZ 1517FCPBGA

The LX2160XC72029B is a high-performance Layerscape microprocessor from NXP Semiconductors featuring a 16-core, 64-bit ARM® Cortex®-A72 architecture running at 2 GHz in a 1517-FCPBGA (40×40) package. Designed for compute-intensive embedded networking and edge processing, this industrial-qualified MPU integrates high-speed I/O, hardware acceleration, and robust memory support to address demanding control and data-plane use cases.

Its combination of multi-core processing, integrated SerDes and Ethernet, and security features makes it suitable for applications that require high throughput, low latency, and reliable operation across a wide temperature range.

Key Features

  • CPU Cores 
    Sixteen ARM® Cortex®-A72 64-bit cores at 2 GHz provide multi-threaded compute capability for packet processing, control-plane tasks, and general-purpose workloads.
  • Memory Subsystem 
    DDR4 memory controller support and family-level details include dual 72-bit DDR4 with ECC up to 3200 MT/s and a maximum capacity referenced at 256 GB, plus on-chip packet cache and a 16 MB cache (as documented in product materials).
  • High-speed SerDes 
    25 GHz SerDes technology with multiple lanes enables high-bandwidth board-level connectivity and system I/O aggregation.
  • Ethernet and Switching 
    Dual 100 Gbit/s Ethernet ports with support for up to 16 Ethernet ports and an integrated Layer 2 switch offering aggregate switching bandwidth suitable for networked and data-center-adjacent designs.
  • Security & Acceleration 
    Integrated security features include Secure Boot and ARM TrustZone®, plus a documented 50 Gbit/s security accelerator for IPsec and related offload tasks.
  • Compression & Offload Engines 
    On-chip data compression/decompression and hardware offload engines are documented to deliver significant throughput for storage and network payload processing.
  • Storage & I/O 
    Four SATA 3.0 ports, 2 × USB 3.0, up to 24 PCIe Gen3 lanes (supporting multi-port configurations), and additional interfaces such as CANbus provide flexible peripheral connectivity.
  • Graphics & Additional Interfaces 
    Graphics acceleration is indicated for display or graphics tasks; additional interfaces include SD, eMMC, DUART, and multiple I2C channels.
  • Package & Reliability 
    1517-ball FCPBGA (40×40) surface-mount package with RoHS compliance and an industrial operating temperature range of −40 °C to 105 °C.

Typical Applications

  • Networking & Routing 
    Control-plane and data-plane processing in edge and carrier networking equipment leveraging multi-core processing and dual 100 Gbit/s Ethernet connectivity.
  • Data Center Offload 
    Application acceleration for compression, security offload and packet processing to reduce host CPU load and improve throughput.
  • 5G Packet Processing 
    Edge and central-unit packet processing for 5G deployments where hardware security and high-speed I/O are required.
  • Industrial Edge Processing 
    High-reliability computing for industrial control, gateway, and aggregation nodes operating across a wide temperature range.
  • Autonomous Systems Compute 
    Sensor and connectivity hub tasks that benefit from parallel cores, integrated I/O, and hardware accelerators for real-time data handling.

Unique Advantages

  • High multiprocessing density: Sixteen 64-bit Cortex‑A72 cores at 2 GHz enable consolidation of multiple workloads onto a single device, reducing board-level BOM and system complexity.
  • Integrated high-speed I/O: Dual 100 Gbit/s Ethernet, SerDes lanes, PCIe Gen3 lanes, SATA and USB connectivity minimize external PHY and bridge requirements for compact system designs.
  • Built-in security and offload: Secure Boot, TrustZone®, and documented security acceleration provide hardware-assisted security and IPsec offload to preserve host CPU cycles.
  • Robust memory and packet handling: DDR4 support with ECC and on-chip packet caching reduce external memory dependency and improve latency for packet-centric workloads.
  • Industrial temperature support: Specified operation from −40 °C to 105 °C enables deployment in demanding environmental conditions.
  • Compact BGA package: 1517-FCPBGA (40×40) surface-mount package allows for high-density placement in constrained system form factors.

Why Choose LX2160XC72029B?

The LX2160XC72029B delivers a balanced combination of multi-core compute, high-speed I/O, integrated accelerators, and security features in an industrial-qualified package. It is positioned for embedded networking, edge compute, and offload designs that need consolidated processing, reduced external components, and predictable operation across wide temperature ranges.

Engineers designing routers, gateways, 5G infrastructure, and edge servers will find the LX2160XC72029B suitable for systems that require throughput, hardware acceleration, and flexible peripheral integration while leveraging NXP’s Layerscape architecture and documented platform capabilities.

Request a quote or submit an inquiry today to evaluate LX2160XC72029B for your next embedded networking or edge processing design.

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