MPC859PVR133A
| Part Description |
MPC8xx Microprocessor IC MPC8xx 1 Core, 32-Bit 133MHz 357-PBGA (25x25) |
|---|---|
| Quantity | 683 Available (as of October 8, 2026) |
| Product Category | Microprocessors |
|---|---|
| Part Series | MPC859 |
| Manufacturer | NXP USA Inc. |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Co-Processors/DSP | Communications; CPM | Core Processor | MPC8xx | Device Package | 357-PBGA (25x25) | ||
|---|---|---|---|---|---|---|---|
| ECCN | 5A991B4B | Ethernet | 10Mbps (1), 10/100Mbps (1) | Graphics Acceleration | No | ||
| HTS Code | 8542.31.0001 | Moisture Sensitivity Level | 3 (168 Hours) | Mounting Method | Surface Mount | ||
| Mounting Type | Surface Mount | Number of Cores/Bus Width | 1 Core, 32-Bit | Operating Temperature | 0°C ~ 95°C (TA) | ||
| Package / Case | 357-BBGA | RAM Controllers | DRAM | REACH Compliance | REACH Unaffected | ||
| RoHS Compliance | ROHS3 Compliant | Speed | 133MHz | Supplier Device Package | 357-PBGA (25×25) | ||
| Voltage – I/O | 3.3V |
Overview of MPC859PVR133A – IC MPU MPC8XX 133MHz 357-PBGA
The MPC859PVR133A is a single‑core, 32‑bit microprocessor in the MPC8xx family, delivering a 133 MHz PowerPC™‑based core optimized for embedded controller and communications systems. It integrates a communications co‑processor (CPM) and peripheral subsystems to support networking and controller applications where integration, deterministic I/O and legacy communications protocols matter.
Designed for surface‑mount deployment in a 357‑pin PBGA (25×25) package and qualified for consumer applications, the device targets embedded networking, communications and control designs requiring a compact, RoHS‑compliant processor solution with broad I/O and memory controller support.
Key Features
- Core & Architecture Embedded single‑issue, 32‑bit PowerPC core with thirty‑two 32‑bit general purpose registers and branch prediction with conditional prefetch as documented for the MPC866/859 family.
- Cache & MMU Implements a 16 KB instruction cache (four‑way set‑associative) and an 8 KB data cache (two‑way set‑associative) for the MPC859P variant; includes MMUs with a 32‑entry TLB and support for multiple page sizes (4, 16 and 512 KB).
- Communications Processor (CPM) Integrated communications co‑processor functionality for offload of protocol handling and serial communications tasks (listed as Communications; CPM in device specifications).
- Networking Interfaces Two Ethernet interfaces: one 10 Mbps port and one 10/100 Mbps port, plus HDLC/SDLC support for framed serial data links.
- Memory Controller On‑chip DRAM controller support to interface with external system memory.
- Power & I/O 3.3 V I/O signaling for compatibility with common embedded peripherals and board designs.
- Package & Mounting 357‑PBGA (25×25) supplier device package; surface mount package suitable for compact board layouts.
- Operating Range & Qualification Rated for an operating temperature range of 0 °C to 95 °C and qualified to consumer product standards. RoHS compliant.
Typical Applications
- Communications Equipment Suitable for controller and networking elements that require integrated Ethernet ports and CPM‑based protocol handling.
- Embedded Controllers Use in dedicated controller applications where a compact single‑core PowerPC processor with DRAM controller is required.
- Networking Appliances Ideal for small networking appliances and gateways that need 10/100 Mbps Ethernet plus legacy 10 Mbps connectivity and HDLC/SDLC support.
Unique Advantages
- Integrated Communications Offload: Built‑in CPM/co‑processor support reduces software overhead for protocol processing and serial communications.
- Balanced On‑Chip Memory Architecture: Combined instruction and data caches with MMU and TLB support improve deterministic performance for embedded workloads.
- Versatile Ethernet Configuration: Dual Ethernet ports (10 Mbps and 10/100 Mbps) provide flexible connectivity options for mixed‑speed network deployments.
- Compact Surface‑Mount Package: 357‑PBGA (25×25) packaging enables dense board layouts while maintaining the I/O and memory interfaces needed by embedded systems.
- RoHS Compliant: Environmentally compliant design supports regulatory requirements for modern electronics manufacturing.
Why Choose MPC859PVR133A?
The MPC859PVR133A brings a PowerPC‑based single‑core implementation with on‑chip communications support and a practical complement of caches, MMU and Ethernet interfaces—delivering a compact, integrated option for embedded communications and controller designs. Its 3.3 V I/O, DRAM controller support and surface‑mount 357‑PBGA package make it straightforward to integrate into space‑constrained boards.
This part is well suited to development teams and procurement looking for a consumer‑qualified, RoHS‑compliant processor that balances compute, deterministic I/O and integrated communications features for networking appliances, controllers and embedded systems where proven architectural features from the MPC866/859 family are required.
Request a quote or submit a pricing and availability inquiry for MPC859PVR133A today to evaluate this processor for your next embedded or communications design.

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