5SGSMD3H2F35C2N
| Part Description |
Stratix® V GS Field Programmable Gate Array (FPGA) IC 432 13312000 236000 1152-BBGA, FCBGA |
|---|---|
| Quantity | 683 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 1152-FBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 1152-BBGA, FCBGA | Number of I/O | 432 | Voltage | 870 mV - 930 mV | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS Compliant | REACH Compliance | REACH Unknown | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 89000 | Number of Logic Elements/Cells | 236000 | ||
| Number of Gates | N/A | ECCN | 3A001A2C | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 13312000 |
Overview of 5SGSMD3H2F35C2N – Stratix® V GS FPGA, 236,000 logic elements, 1152‑BBGA
The 5SGSMD3H2F35C2N is an Intel Stratix V GS field-programmable gate array (FPGA) optimized for transceiver‑based, DSP‑centric designs. Built on a 28‑nm process and featuring a redesigned adaptive logic module (ALM) and rich hard-IP, this device targets high-throughput signal processing and connectivity applications.
With 236,000 logic elements, approximately 13.3 Mbits of embedded memory, abundant DSP resources and integrated transceivers, this device is suited for wireline, broadcast, high‑performance computing and other systems requiring dense logic, high‑precision DSP, and substantial I/O connectivity.
Key Features
- Process and Core Architecture 28‑nm TSMC process with a redesigned adaptive logic module (ALM) for optimized logic density and routing.
- Logic Capacity 236,000 logic elements providing substantial programmable fabric for complex designs.
- Embedded Memory Approximately 13.3 Mbits of on‑chip RAM organized as 20 Kbit (M20K) memory blocks for buffering and state storage.
- High‑Precision DSP Blocks Variable‑precision DSP resources; Stratix V GS devices support up to 3,926 18×18 or 1,963 27×27 multipliers for intensive arithmetic and signal processing tasks.
- Integrated Transceivers & I/O GS‑variant transceivers with 14.1 Gbps capability and support for backplane and optical interfaces, plus 432 general I/Os for system connectivity.
- Clocking and Hard IP Fractional PLLs for flexible clocking and an Embedded HardCopy Block for hardening IP such as PCIe Gen1/Gen2/Gen3 instantiations.
- Package, Power and Mounting 1152‑BBGA FCBGA package (supplier: 1152‑FBGA, 35×35), surface‑mount; core supply range 870 mV to 930 mV; RoHS compliant.
- Operating Range Rated for commercial operating temperatures from 0 °C to 85 °C.
Typical Applications
- Wireline and Networking: High‑throughput packet processing and transport systems that require large logic capacity and integrated transceivers for backplane and optical interfaces.
- Broadcast and Optical Systems: DSP‑intensive modulation, filtering and signal aggregation tasks that benefit from abundant DSP multipliers and on‑chip memory.
- High‑Performance Computing: Acceleration of compute kernels and data‑path processing using variable‑precision DSP blocks and dense logic fabric.
- Defense and Communications: Real‑time signal processing and transceiver integration for communications equipment used in demanding signal chain applications.
- ASIC Prototyping and Migration: Prototype designs with a documented path to HardCopy V ASICs for volume production and risk reduction.
Unique Advantages
- Substantial Logic and Memory: 236,000 logic elements combined with approximately 13.3 Mbits of embedded RAM support large, complex designs without excessive external memory.
- DSP‑Focused Architecture: Thousands of variable‑precision DSP multipliers enable high‑precision and high‑throughput signal processing implementations.
- Integrated High‑Speed I/O: 432 I/Os plus GS transceivers with 14.1 Gbps capability simplify system partitioning and reduce external PHY requirements.
- Hard IP and Clocking: Embedded HardCopy Block for hardened IP instantiation and fractional PLLs for flexible, precise clock management.
- Commercial‑Grade Availability: Commercial operating range and RoHS compliance for mainstream electronic applications.
- Production Migration Path: Designed within the Stratix V family to support prototyping and a low‑risk route to HardCopy V ASICs for production scaling.
Why Choose 5SGSMD3H2F35C2N?
The 5SGSMD3H2F35C2N positions itself where dense programmable logic, extensive on‑chip memory and powerful DSP resources meet integrated transceiver capability. It is a suitable choice for engineers building DSP‑heavy, transceiver‑enabled systems that require high logic capacity and flexible clocking.
This Stratix V GS device offers a clear path from prototype to production thanks to the family’s Embedded HardCopy Block and documented migration options, providing scalability and investment protection for long‑lifecycle projects.
Request a quote or submit an inquiry to evaluate the 5SGSMD3H2F35C2N for your next design and obtain pricing and availability details.

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