AT40K40-2BGC
| Part Description |
AT40K/KLV Field Programmable Gate Array (FPGA) IC 289 18432 2304 352-LBGA |
|---|---|
| Quantity | 594 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Microchip Technology |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 352-SBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 352-LBGA | Number of I/O | 289 | Voltage | 4.75 V - 5.25 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 2304 | Number of Logic Elements/Cells | 2304 | ||
| Number of Gates | 50000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 18432 |
Overview of AT40K40-2BGC – AT40K/KLV Field Programmable Gate Array (FPGA) 352-LBGA
The AT40K40-2BGC is an SRAM-based FPGA offered in a 352-ball LBGA package that delivers 2,304 logic elements, 18,432 bits of distributed on-chip RAM, and up to 289 I/Os. Built for commercial applications, it operates from a 4.75 V to 5.25 V supply and across a 0 °C to 70 °C temperature range.
Part of the AT40K family, this device targets high-performance logic and DSP-oriented designs that benefit from fast embedded memory, multiple global clocks and in-system reconfigurability for adaptive or updateable designs.
Key Features
- Core Performance – Ultra-high-performance architecture with system speeds to 100 MHz and support for array multipliers enabling arithmetic-intensive operations.
- Logic Capacity – 2,304 logic elements (cells) providing approximately 50,000 usable gates for medium-to-large FPGA implementations.
- Distributed On-Chip Memory (FreeRAM) – 18,432 bits of flexible 10 ns SRAM that can be instantiated as single- or dual-port, synchronous or asynchronous RAM without consuming additional logic resources.
- I/O Flexibility – Up to 289 I/Os with series-level support for 3 V/5 V signaling options and programmable output drive; aligns with the family’s 128–384 I/O range for varied interface requirements.
- Clocking – Eight global clocks with low-skew distribution, programmable edge transitions and distributed clock shutdown for power management.
- In-System Reconfigurability (Cache Logic) – Supports dynamic full or partial reconfiguration via serial or parallel modes for adaptive designs and in-field updates.
- Package & Mounting – 352-LBGA (352-SBGA, 35×35) surface-mount package for compact board integration.
- Commercial Grade & Compliance – Commercial temperature grade (0 °C to 70 °C) and RoHS compliant.
Typical Applications
- DSP Co-processor: Implement FIR filters, FFTs and other arithmetic-heavy functions using the device’s array multipliers and distributed memory for high-throughput signal processing.
- Video and Multimedia Processing: Support video compression/decompression and related transforms by leveraging fast on-chip RAM and hardware multiplier resources.
- High-Speed Interface Bridging: Use the abundant I/Os and programmable output drive for protocol bridging, custom interface logic or peripheral aggregation.
- Adaptive/Field-Upgradeable Systems: Employ Cache Logic reconfiguration to update algorithms, coefficients or partial designs in-system without disrupting retained data.
Unique Advantages
- Balanced Logic and Memory: 2,304 logic elements paired with 18,432 bits of distributed RAM enable compact implementations of processors, buffers and FIFOs without external RAM.
- Fast On-Chip SRAM: 10 ns FreeRAM supports low-latency data paths for DSP and buffering tasks, reducing system-level latency compared to off-chip options.
- Flexible Clocking: Eight global clocks with programmable edges and shutdown provide fine-grained timing control and opportunities for power reduction during idle periods.
- In-System Reprogramming: Serial and parallel reconfiguration modes allow iterative development and field updates, supporting adaptive algorithms and post-deployment fixes.
- Compact BGA Package: 352-ball LBGA (35×35) provides high I/O density in a compact footprint for space-constrained boards.
Why Choose AT40K40-2BGC?
The AT40K40-2BGC combines a mid-to-high gate-count FPGA fabric with substantial distributed SRAM and flexible I/O to address designs that require on-chip memory, DSP acceleration and field programmability. Its eight global clocks and reconfiguration capabilities make it suitable for systems that need deterministic timing and in-field adaptability.
Ideal for engineering teams building commercial-grade signal processing, interface and adaptive logic applications, the AT40K40-2BGC offers a balance of performance, integration and board-level density while adhering to RoHS requirements and standard surface-mount assembly practices.
Request a quote or submit your procurement inquiry to receive pricing and availability for the AT40K40-2BGC. Our team can assist with volume pricing and lead-time details to support your project schedule.

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