EP20K30ETC144-3

IC FPGA 92 I/O 144TQFP
Part Description

APEX-20KE® Field Programmable Gate Array (FPGA) IC 92 24576 1200 144-LQFP

Quantity 372 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerIntel
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package144-TQFP (20x20)GradeCommercialOperating Temperature0°C – 85°C
Package / Case144-LQFPNumber of I/O92Voltage1.71 V - 1.89 V
Mounting MethodSurface MountRoHS ComplianceRoHS non-compliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs120Number of Logic Elements/Cells1200
Number of Gates113000ECCN3A991DHTS Code8542.39.0001
QualificationN/ATotal RAM Bits24576

Overview of EP20K30ETC144-3 – APEX-20KE FPGA, 1,200 logic elements, 24,576-bit RAM, 144-LQFP

The EP20K30ETC144-3 is an APEX-20KE family field programmable gate array supplied in a 144-LQFP surface-mount package. It combines a MultiCore architecture with embedded system blocks (ESBs) to implement on-chip memory and product-term logic, enabling compact system integration for commercial embedded applications.

With 1,200 logic elements, 24,576 bits of embedded RAM, and 92 user I/O pins in a 144-pin footprint, this device targets designs that require moderate programmable logic capacity, flexible I/O interfacing and on-chip memory resources within a commercial temperature range.

Key Features

  • Programmable Logic Core  MultiCore architecture with look-up table (LUT) logic and product-term logic for register- and combinatorial-intensive functions; 1,200 logic elements and approximately 113,000 maximum system gates.
  • Embedded Memory (ESBs)  24,576 total RAM bits implemented as embedded system blocks suitable for FIFOs, dual-port RAM or content-addressable memory functions.
  • I/O Capacity & Flexibility  92 user I/O pins with MultiVolt I/O interface support for 1.8 V, 2.5 V, 3.3 V and 5.0 V signalling levels (series-level support), and programmable slew-rate and clamp options described in the APEX 20K family documentation.
  • Clock Management  Series-level clock features include up to four phase-locked loops (PLLs), a built-in low-skew clock tree and support for up to eight global clock signals for predictable timing distribution.
  • Package & Mounting  144-LQFP package (supplier device package: 144-TQFP 20×20) designed for surface-mount assembly in compact board layouts.
  • Power & Supply  Internal supply operation around 1.71 V to 1.89 V (device specification); APEX 20K family supports low-power modes and multi-voltage I/O interfacing.
  • Commercial Temperature Grade  Rated for operation from 0 °C to 85 °C for standard commercial applications.
  • Standards & Performance (Series-Level)  APEX 20K family documentation details support for high-speed external memories (including DDR SDRAM and ZBT SRAM), PCI Local Bus 2.2 compliance at 3.3 V, and LVDS performance described for series devices.

Typical Applications

  • Embedded controllers  Implement control logic, state machines and interface bridging in compact commercial systems using on-chip RAM and LUT-based logic.
  • Memory interface and buffering  Use ESBs to build FIFOs, dual-port RAM or buffering elements for systems that require moderate on-chip memory.
  • High-speed I/O aggregation  Integrate multi-voltage I/O and differential signalling in applications that need flexible connectivity and protocol bridging.
  • Prototyping and evaluation  Suitable for development platforms and proof-of-concept designs that require reprogrammable logic in a 144-LQFP footprint.

Unique Advantages

  • Compact, surface-mount package: Enables space-efficient PCB layouts with a 144-LQFP (144-TQFP 20×20) package while providing 92 user I/O pins.
  • Integrated embedded memory: 24,576 bits of on-chip RAM implemented as ESBs reduce the need for external memory for modest buffering and storage tasks.
  • Flexible I/O voltage support: Series MultiVolt I/O capability allows interfacing with a wide range of logic levels, simplifying mixed-voltage board designs.
  • Deterministic clocking options: PLLs, low-skew clock tree and multiple global clock signals support predictable timing distribution for synchronous designs.
  • Commercial-grade operating range: Rated 0 °C to 85 °C to suit mainstream embedded and industrial-commercial applications.

Why Choose EP20K30ETC144-3?

The EP20K30ETC144-3 delivers a balanced combination of reprogrammable logic, embedded memory and flexible I/O in a small 144-LQFP package suited to commercial designs. Its APEX-20KE family architecture provides LUT-based logic and ESB memory blocks that simplify integration of control, buffering and interface functions on a single device.

This device is well matched to engineers developing compact embedded systems, interface controllers, and evaluation platforms that require moderate logic density, on-chip RAM and multi-voltage I/O capability while operating within a commercial temperature range.

Request a quote or submit an inquiry to receive pricing and availability information for the EP20K30ETC144-3.

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