EP20K400BC652-2
| Part Description |
APEX-20K® Field Programmable Gate Array (FPGA) IC 502 212992 16640 652-BGA |
|---|---|
| Quantity | 964 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 652-BGA (45x45) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 652-BGA | Number of I/O | 502 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1664 | Number of Logic Elements/Cells | 16640 | ||
| Number of Gates | 1052000 | ECCN | 3A001A2A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 212992 |
Overview of EP20K400BC652-2 – APEX-20K® Field Programmable Gate Array (FPGA), 652-BGA
The EP20K400BC652-2 is an APEX-20K family FPGA optimized for high-density, system-level integration. It implements a MultiCore architecture combining look-up table (LUT) logic, product-term logic and embedded memory to support complex, register- and memory-intensive designs.
With 16,640 logic elements, approximately 0.213 Mbits of embedded memory, 502 I/O and roughly 1,052,000 gates, this commercial-grade, surface-mount device targets applications that require significant logic density, flexible I/O and advanced clock management while operating over a 0 °C to 85 °C range.
Key Features
- Core Architecture MultiCore architecture integrating LUT logic, product-term logic and embedded system blocks for efficient implementation of both register-intensive and combinatorial functions.
- Logic Capacity 16,640 logic elements providing approximately 1,052,000 gates of logic capacity for high-density designs.
- Embedded Memory Total on-chip RAM of 212,992 bits (approximately 0.213 Mbits) for FIFOs, dual-port RAM and CAM implementations.
- I/O and Interface Flexibility 502 user I/O pins with MultiVolt I/O interface support and features such as programmable clamp, individual tri-state enable and programmable output slew-rate control.
- High‑Speed I/O Capabilities Support for high-speed external memories including DDR SDRAM and ZBT SRAM; bidirectional I/O performance (tCO + tSU) up to 250 MHz and LVDS performance up to 840 Mbit/s per channel as specified for the APEX 20K family.
- Clock Management Flexible clock circuitry with up to four PLLs, up to eight global clock signals, and features including ClockLock, ClockBoost and ClockShift for phase and delay control.
- Power and Supply Internal supply operation consistent with the family and a specified supply range of 2.375 V to 2.625 V for this device.
- Package and Thermal 652-ball BGA package (45×45 mm) in a surface-mount form factor; commercial operating temperature range 0 °C to 85 °C.
- Compliance RoHS compliant.
Typical Applications
- Telecommunications and Networking Dense logic and high-speed I/O support implementations of protocol processing, packet forwarding and memory‑buffered data paths.
- High‑Speed Memory Interfaces Use as a controller or interface glue for DDR SDRAM and ZBT SRAM applications where embedded RAM and flexible I/O are required.
- Custom Embedded Systems Implement custom datapaths, control logic and FIFO buffering using the device’s logic elements and embedded memory blocks.
- Prototyping and System Integration Leverage the MultiCore architecture and programmable clock features to prototype SOPC-style integration of logic and memory functions.
Unique Advantages
- Highly integrated architecture: MultiCore design with LUTs, product-term logic and embedded system blocks reduces external component count for memory‑centric functions.
- Substantial logic and memory resources: 16,640 logic elements and approximately 0.213 Mbits of on-chip RAM enable complex functions and local buffering without off-chip memory for many use cases.
- Broad I/O capability: 502 I/O pins with MultiVolt support and programmable I/O options provide flexibility for mixed-voltage systems and a wide range of interface standards.
- Advanced clock control: Up to four PLLs and dedicated clock features (ClockLock, ClockBoost, ClockShift) enable precise clocking strategies for synchronous designs.
- Commercial temperature and packaging: Surface-mount 652-BGA (45×45) package with 0 °C to 85 °C rating for deployment in commercial electronic systems.
- Standards-oriented I/O: Family-level support for interfaces such as LVDS and PCI (3.3 V operation) helps integrate with common system buses and high-speed links.
Why Choose EP20K400BC652-2?
The EP20K400BC652-2 delivers a balance of high logic density, embedded memory and flexible I/O in the APEX-20K family architecture. It is well suited to engineers specifying a commercial‑grade FPGA that must implement dense logic, on-chip buffering and advanced clocking within a 652-BGA package.
For designs that require scalable logic capacity, substantial embedded RAM and a wide complement of I/O, this device offers a proven architecture and the programmable resources needed to consolidate functions and streamline system implementation.
Request a quote or submit a quote today to check pricing and availability for the EP20K400BC652-2.

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