EP20K60ETC144-2
| Part Description |
APEX-20KE® Field Programmable Gate Array (FPGA) IC 92 32768 2560 144-LQFP |
|---|---|
| Quantity | 773 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 144-TQFP (20x20) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 144-LQFP | Number of I/O | 92 | Voltage | 1.71 V - 1.89 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 2560 | Number of Logic Elements/Cells | 2560 | ||
| Number of Gates | 162000 | ECCN | 3A001A2A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 32768 |
Overview of EP20K60ETC144-2 – APEX-20KE® Field Programmable Gate Array (FPGA) IC 92 32768 2560 144-LQFP
The EP20K60ETC144-2 is an APEX-20KE family FPGA offering a balanced mix of logic, embedded memory, and I/O in a compact 144-LQFP package. Built on the APEX 20K MultiCore architecture, the device integrates look-up table (LUT) logic, product-term logic and embedded system blocks (ESBs) to support register‑intensive and memory‑centric functions.
Targeted at commercial designs that require moderate logic density and on-chip RAM, this device delivers 2,560 logic elements, 32,768 bits of embedded RAM and 92 user I/O pins while operating from a 1.71 V–1.89 V supply and a 0 °C–85 °C operating range.
Key Features
- Core architecture: APEX-20KE MultiCore architecture integrating LUT logic, product-term logic and embedded memory to support a mix of register‑intensive and combinatorial functions.
- Logic capacity: 2,560 logic elements providing a deployable logic fabric for mid‑scale programmable designs; approximately 162,000 maximum system gates as defined for this class.
- Embedded memory: 32,768 total RAM bits suitable for FIFOs, small buffers and dual‑port RAM implementations using ESBs.
- I/O and interfacing: 92 user I/O pins to connect external peripherals and memory interfaces; family-level support for a wide range of I/O standards is provided by the APEX 20K architecture.
- Clocking and timing: APEX 20K family clock management features such as PLLs, a low‑skew clock tree and multiple global clocks (documented at the family level) to support synchronous designs.
- Package and mounting: Surface-mount 144-LQFP package (supplier device package listed as 144‑TQFP, 20×20) for PCB integration in space-efficient board layouts.
- Power and temperature: Internal supply range 1.71 V–1.89 V and commercial operating temperature range from 0 °C to 85 °C.
- Standards and compliance: RoHS compliant, supporting regulatory and environmental requirements for commercial products.
Typical Applications
- Networking and Communications: Implement protocol bridging, packet buffering and interface logic using on‑chip ESBs and moderate logic capacity.
- Memory Interface and Buffering: Use embedded RAM and ESB features to create FIFO buffers, dual‑port RAM or small memory controllers for external memory subsystems.
- Embedded Systems and Prototyping: Rapidly iterate custom logic, peripheral glue and system integration functions in commercial equipment and development platforms.
- High‑speed I/O Subsystems: Leverage the device’s I/O count and APEX family I/O capabilities for interfacing with a variety of voltage levels and high‑speed signaling standards supported by the family.
Unique Advantages
- Balanced logic and memory: Combines 2,560 logic elements with 32,768 bits of embedded RAM to implement mixed compute-and-buffer designs without external memory for small data sets.
- Integrated MultiCore architecture: Family-level MultiCore integration of LUTs, product-term logic and ESBs enables efficient mapping of both register-intensive and memory-centric functions.
- Flexible clock management: APEX 20K family clock features such as PLLs and a low‑skew clock tree help simplify timing closure for multi‑clock designs.
- Compact, surface-mount package: 144-LQFP (144‑TQFP 20×20 supplier designation) supports dense PCB designs while providing ample I/O for mid-scale systems.
- Commercial-grade operation: 1.71 V–1.89 V supply operation and 0 °C–85 °C temperature range make the device suitable for a wide range of commercial electronic products.
Why Choose EP20K60ETC144-2?
The EP20K60ETC144-2 provides a practical combination of logic elements, embedded RAM and I/O in a compact LQFP package for commercial FPGA applications. Its APEX-20KE family architecture supports both register-intensive and memory-focused implementations, making it well suited for communications logic, embedded control and mid-scale prototyping tasks.
For teams building commercial equipment that require on-chip FIFOs, dual-port RAM, moderate logic density and flexible I/O, this device delivers a focused feature set with RoHS compliance and a standard commercial temperature rating.
Request a quote or submit a purchasing inquiry to evaluate the EP20K60ETC144-2 for your next design.

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