LFE3-35EA-6FN672C
| Part Description |
ECP3 Field Programmable Gate Array (FPGA) IC 310 1358848 33000 672-BBGA |
|---|---|
| Quantity | 337 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 20 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FPBGA (27x27) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 310 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | ROHS3 Compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 4125 | Number of Logic Elements/Cells | 33000 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 1358848 |
Overview of LFE3-35EA-6FN672C – ECP3 FPGA, 33,000 logic elements, 310 I/Os, 672-BBGA
The LFE3-35EA-6FN672C is a Field Programmable Gate Array (FPGA) IC from Lattice Semiconductor’s ECP3 family, designed for commercial applications requiring high logic density and extensive I/O. Built on the ECP3 architecture, this device delivers a balance of embedded memory, DSP-friendly fabric features, and flexible I/O in a compact 672-ball FBGA package.
Key Features
- Logic Capacity Approximately 33,000 logic elements for implementing complex digital functions and glue logic in a single device.
- Embedded Memory Approximately 1.36 Mbits of on-chip RAM (1,358,848 bits) to support buffering, state storage, and local data processing.
- I/O and Package 310 user I/Os in a 672-ball FPBGA package (27 × 27 mm), enabling high-pin-count, high-density system integration. Mounting is surface-mount.
- Power Core voltage supply range from 1.14 V to 1.26 V for predictable power delivery and system design consistency.
- Operating Range Commercial temperature grade with an operating range of 0 °C to 85 °C.
- Family-Level Architecture Built on the Lattice ECP3 family architecture that includes embedded SERDES, sysDSP slice support, PLL/DLL clock management, and flexible source-synchronous I/O (features described at the family level in the datasheet).
- Compliance RoHS compliant.
Typical Applications
- Communications Modules High I/O count and family-level SERDES support make this FPGA suitable for I/O-intensive communications interface and protocol bridging tasks.
- Embedded Processing On-chip RAM and the ECP3 family’s DSP-oriented features support local data buffering and signal processing functions in commercial embedded systems.
- Prototyping and Production Compact 672-BBGA packaging and 33,000 logic elements provide a practical platform for scaling from prototype to volume commercial deployments.
Unique Advantages
- High Logic Density: Approximately 33,000 logic elements let you consolidate multiple functions into a single device, reducing board-level BOM and complexity.
- Substantial On-Chip RAM: Approximately 1.36 Mbits of embedded memory supports larger local buffers and state machines without immediate need for external memory.
- Broad I/O Count in Compact Package: 310 I/Os in a 672-ball FPBGA (27 × 27 mm) provide extensive connectivity while keeping PCB footprint manageable.
- Commercial Temperature Suitability: Rated 0 °C to 85 °C for reliable operation in standard commercial environments.
- Family Architecture Benefits: Leverages ECP3 family capabilities—such as DSP slices, PLL/DLL clocking, and high-speed serial support at the family level—to simplify integration of timing-critical and signal-processing functions.
- RoHS Compliant: Meets RoHS requirements for environmentally conscious designs.
Why Choose LFE3-35EA-6FN672C?
The LFE3-35EA-6FN672C positions itself as a practical choice for commercial designs that require a combination of mid-to-high logic capacity, significant on-chip memory, and a large number of I/Os in a compact surface-mount package. Its alignment with the Lattice ECP3 family architecture provides access to DSP-oriented resources, clock management, and family-level high-speed interface support.
This part is well suited for development teams and producers of commercial electronic systems who need scalable logic resources, plentiful connectivity, and predictable operating conditions backed by the documented capabilities of the ECP3 family.
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