LFE3-35EA-6FN672I

The LFE3-35EA-6FN672I is a Lattice Semiconductor ECP3 family FPGA supplied in a 672-BBGA (27 × 27 mm) package. It provides a mid-density, reconfigurable SRAM-based fabric optimized for high-performance signal processing, source-synchronous interfaces and embedded communications functions.

With 33,000 logic elements, approximately 1.36 Mbits of embedded memory, and 310 user I/Os, this industrial-grade device targets demanding embedded and communications applications that require a balance of integration, I/O capacity and configurability. The device operates from a core supply range of 1.14 V to 1.26 V and supports operation from -40 °C to 100 °C. It is RoHS compliant.

Key Features

• Logic Capacity  33,000 logic elements for implementing mid-density FPGA designs and complex state machines.
• Embedded Memory  Approximately 1.36 Mbits of on-chip RAM for buffering, frame storage and algorithm state.
• I/O and Package  310 user I/Os in a 672-FPBGA (27 × 27 mm) surface-mount package to support wide external interfacing and high pin-count systems.
• Industrial Operating Range  Qualified for industrial temperature operation from -40 °C to 100 °C.
• Low-Voltage Core  Core voltage supply range of 1.14 V to 1.26 V to match modern low-voltage power domains.
• Family-Level SERDES and High-Speed I/O  LatticeECP3 family features include embedded SERDES with multi-hundred Mbps to multiple-Gbps capability and a programmable sysI/O buffer supporting a broad range of I/O standards for source-synchronous interfaces (as described in the family datasheet).
• DSP and Clock Resources  The ECP3 family provides enhanced DSP slice architecture and multiple PLL/DLL resources for high-performance multiply-accumulate and clock management functions (family-level features from the ECP3 datasheet).
• Configuration and System Support  Family-level support for flexible configuration modes, SPI boot, dual-boot images and system utilities referenced in the ECP3 datasheet. Device is RoHS compliant.

Typical Applications

• High-speed communications  Use the device where embedded SERDES and source-synchronous I/O are required for protocols such as Ethernet, PCI Express and other serial links supported by the ECP3 family.
• Video and broadcast interfaces  Implement SMPTE or other high-throughput video interfaces using the device’s I/O capacity and DSP resources.
• Signal processing and analytics  Deploy sysDSP slices and on-chip memory for real-time filtering, aggregation and multiply-accumulate operations.
• Memory controller and buffering  Leverage the embedded memory and configurable I/O to implement DDR/DDR2/DDR3 interfaces and buffering schemes (family-level memory interface support documented in the datasheet).

Unique Advantages

• Balanced integration: Combines 33,000 logic elements with substantial embedded RAM and 310 I/Os to reduce external glue logic and simplify system design.
• Industrial temperature capability: Rated for -40 °C to 100 °C operation to meet a wide range of industrial application environments.
• Compact, high-pin-count package: 672-FPBGA (27 × 27 mm) surface-mount package supports high I/O density while remaining suitable for compact board layouts.
• Low-voltage core compatibility: 1.14 V to 1.26 V supply range aligns with modern low-voltage system domains.
• Proven ECP3 family feature set: Access to family-level features such as SERDES, sysDSP, PLL/DLL clocking and flexible sysI/O for a broad set of interface and processing tasks (see ECP3 family datasheet for full details).

Why Choose LFE3-35EA-6FN672I?

The LFE3-35EA-6FN672I positions itself as a versatile mid-density FPGA solution for embedded systems that require a combination of sizable logic resources, appreciable embedded memory and abundant I/O. Its industrial temperature rating and RoHS compliance make it suitable for long-life industrial deployments, while the ECP3 family architecture provides DSP, clocking and high-speed I/O capabilities referenced in the family datasheet.

This part is appropriate for engineers designing communications, video, signal processing and memory-interface systems that benefit from integrated SERDES and DSP resources, a high I/O count, and a compact 672-BBGA footprint. The ECP3 family ecosystem documented in the datasheet supports development and system integration needs.

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