LFECP33E-3FN672I
| Part Description |
ECP Field Programmable Gate Array (FPGA) IC 496 434176 32800 672-BBGA |
|---|---|
| Quantity | 1,694 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FPBGA (27x27) | Grade | Industrial | Operating Temperature | -40°C – 100°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 496 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 4096 | Number of Logic Elements/Cells | 32800 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 434176 |
Overview of LFECP33E-3FN672I – ECP FPGA, 672-BBGA, 496 I/O
The LFECP33E-3FN672I is a Field Programmable Gate Array (FPGA) IC based on the LatticeECP family architecture. It delivers a high logic density device with integrated memory and flexible I/O in a compact 672-ball FPBGA package for mainstream and industrial embedded applications.
Designed for cost-sensitive, performance-oriented designs, this device combines approximately 32,800 logic elements with approximately 0.43 Mbits of on-chip RAM, extensive I/O capability, and family-level DSP, clocking and memory-interface features to support signal processing, interface bridging and system-control functions.
Key Features
- Core Logic Density — 32,800 logic elements provide substantial capacity for mid- to high-density designs.
- Embedded Memory — Total on-chip RAM of 434,176 bits (approximately 0.43 Mbits) for block and distributed memory use.
- High I/O Count — 496 user I/Os for wide parallel interfaces, board-level connectivity and multi-protocol support.
- Family DSP Capability — LatticeECP family sysDSP blocks (family-level feature) support high-performance multiply-accumulate implementations with configurations such as 4–8 36×36 multipliers or alternative multiplier arrangements.
- Flexible I/O Standards — Family-level programmable I/O buffer support includes LVCMOS (3.3/2.5/1.8/1.5/1.2), LVTTL, SSTL, HSTL, PCI, LVDS, LVPECL and RSDS for diverse interface requirements.
- Dedicated DDR Support — Family-level dedicated DDR memory interface logic supports implementations up to DDR400 (200 MHz).
- Clocking — Family-level support for up to four analog PLLs for clock multiply/divide and phase shifting.
- Power and Mounting — Low-voltage core operation with a supply range of 1.14 V to 1.26 V; surface-mount package.
- Package and Thermal — 672-ball FPBGA (27 × 27 mm) package; rated operating temperature range −40 °C to 100 °C and specified as Industrial grade.
- Compliance — RoHS compliant.
Typical Applications
- DSP-accelerated signal processing — Use the family-level sysDSP resources and on-chip memory for FIR/IIR, filtering and other high-throughput arithmetic tasks.
- High-density I/O bridging — The 496 I/Os and flexible I/O standards enable protocol translation and multi-channel interface aggregation.
- Embedded control and industrial systems — Industrial temperature rating and compact 672-FPBGA package make it suitable for industrial automation, motor control and factory instrumentation.
- Memory interface designs — Dedicated DDR interface support facilitates designs requiring external DDR memory for buffering and system memory.
Unique Advantages
- High logic capacity: 32,800 logic elements support complex logic integration and feature-rich designs without external glue logic.
- Substantial on-chip RAM: Approximately 0.43 Mbits of embedded memory reduces external memory dependency for many control and buffering tasks.
- Extensive I/O flexibility: 496 I/Os with family-level multi-standard support simplifies multi-protocol designs and reduces adapter components.
- Industrial temperature range: −40 °C to 100 °C operation supports deployments in demanding environments.
- Compact, board-friendly package: 672-ball FPBGA (27 × 27 mm) delivers high density in a standard surface-mount form factor.
- Design ecosystem support: LatticeECP family-level support with ispLEVER design tools and predesigned ispLeverCORE IP modules streamlines development and accelerates time to prototype.
Why Choose LFECP33E-3FN672I?
The LFECP33E-3FN672I positions itself as a mid- to high-density FPGA option within the LatticeECP family, combining significant logic resources, on-chip memory and a large, flexible I/O fabric in a compact 672-FPBGA package. Its low-voltage core and family-level DSP and DDR interface capabilities make it well suited to engineers building signal processing, interface and embedded-control solutions for industrial and mainstream markets.
Supported by the LatticeECP family design ecosystem and RoHS compliance, this device offers a balanced platform for projects that require integrated performance, scalability and established toolchain support.
If you would like pricing, lead time or to request a quote for the LFECP33E-3FN672I, submit an RFQ or request a quote to receive availability and purchasing details.

Date Founded: 1983
Headquarters: Hillsboro, Oregon, USA
Employees: 1,000+
Revenue: $627.7 Million
Certifications and Memberships: ISO9001:2015, ISO14001:2015, IATF16949:2016