XCV400-5BG560C
| Part Description |
Virtex® Field Programmable Gate Array (FPGA) IC 404 81920 10800 560-LBGA Exposed Pad, Metal |
|---|---|
| Quantity | 31 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | AMD |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 560-MBGA (42.5x42.5) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 560-LBGA Exposed Pad, Metal | Number of I/O | 404 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 2400 | Number of Logic Elements/Cells | 10800 | ||
| Number of Gates | 468252 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 81920 |
Overview of XCV400-5BG560C – Virtex® Field Programmable Gate Array (FPGA), 10,800 Logic Elements, 404 I/O, 560-LBGA
The XCV400-5BG560C is a Virtex® SRAM-based FPGA offering high-density programmable logic in a 560-LBGA exposed-pad package. It provides 10,800 logic elements, approximately 81,920 bits of embedded memory, and 404 user I/O, making it suitable for high-performance digital designs and configurable system logic.
Built on the Virtex family architecture, this commercial-grade device targets applications that require flexible I/O, hierarchical on-chip memory, and reprogrammable system configuration while operating within a 2.375 V to 2.625 V supply range and a 0 °C to 85 °C commercial temperature window.
Key Features
- Logic Capacity — 10,800 logic elements and 468,252 system gates support complex combinational and sequential designs.
- On-Chip Memory — Approximately 81,920 bits of embedded RAM with hierarchical memory options including LUT-configurable RAM and configurable 4k-bit dual-ported RAMs.
- High-Density I/O — 404 available I/O pins with multi-standard SelectIO™ support and 16 high-performance interface standards for diverse board-level connectivity.
- Clocking and Timing — Four dedicated delay-locked loops (DLLs), four primary low-skew global clock nets and 24 secondary local clock nets for advanced clock management.
- Arithmetic and DSP Support — Dedicated carry logic, multiplier support, and cascade chains for wide-input functions accelerate arithmetic and signal-processing implementations.
- Configuration Flexibility — SRAM-based in-system configuration with unlimited re-programmability and multiple programming modes for iterative development and field updates.
- Package and Mounting — 560-LBGA exposed pad, metal (supplier package: 560-MBGA, 42.5 × 42.5 mm); surface-mount mounting for compact board integration.
- Power and Environmental — Operating supply voltage 2.375 V to 2.625 V; commercial operating temperature 0 °C to 85 °C; RoHS compliant.
- System and Test Features — IEEE 1149.1 boundary-scan support, die-temperature sensor diode, and 100% factory testing.
Typical Applications
- PCI and CompactPCI Systems — 66‑MHz PCI compliance and hot‑swappable support enable use in modular I/O and communication backplanes.
- High-Performance Signal Processing — Dedicated multipliers, carry chains and abundant registers suit DSP algorithms and custom accelerators.
- Protocol Bridging and I/O Aggregation — Multi-standard SelectIO and 404 I/O support implement protocol conversion, interface bridging and custom peripheral controllers.
- Embedded System Prototyping — SRAM-based, reprogrammable configuration supports iterative development, in-system updates and proof-of-concept designs.
Unique Advantages
- Significant Logic Density: 10,800 logic elements and 468,252 gates provide ample capacity for medium-to-large FPGA designs without external logic.
- Rich On-Chip Memory: Approximately 81,920 bits of embedded RAM and LUT-configurable memory reduce dependence on external RAM for many buffering and local storage tasks.
- Flexible Clocking: Multiple DLLs and hierarchical clock nets enable refined clock control for timing-critical designs.
- Versatile I/O Options: 404 I/O with SelectIO multi-standard support simplifies interfacing to a wide range of peripherals and standards.
- In-System Reprogrammability: SRAM configuration with multiple programming modes supports iterative design flows and field updates.
- Commercial Temperature and Compliance: Designed for 0 °C to 85 °C operation and RoHS compliance for standard commercial deployments.
Why Choose XCV400-5BG560C?
The XCV400-5BG560C combines a proven Virtex architecture with substantial logic, memory and I/O resources to address demanding digital, communication and control applications. Its clocking resources, arithmetic support and flexible on-chip memory enable efficient implementation of complex algorithms while retaining the advantages of SRAM-based reprogrammability.
Engineers and integrators seeking a commercial-grade, mid-to-high density FPGA with strong development support and configurable system features can leverage this device for rapid prototyping, in-field updates and compact board-level integration thanks to its 560-LBGA surface-mount package.
Request a quote or submit a pricing inquiry to receive availability and ordering information for the XCV400-5BG560C.

Date Founded: 1969
Headquarters: Santa Clara, California, USA
Employees: 25,000+
Revenue: $22.68 Billion
Certifications and Memberships: ISO9001:2015, RoHS, REACH








