M15T2G16128A-BDBG2P

2Gb DDR3L SDRAM Ind.
Part Description

DDR3L SDRAM 2Gb 128Mbx16 800MHz DDR3(L)-1600 96 Ball BGA

Quantity 630 Available (as of May 5, 2026)
Product CategoryMemory
ManufacturerESMT
Manufacturing StatusMP
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package96 Ball BGAMemory FormatDRAMTechnologyDDR3L
Memory Size2 GbitAccess Time13.75 nsGradeIndustrial
Clock Frequency800 MHzVoltage1.35V, 1.5VMemory TypeVolatile
Operating Temperature-40°C – 95°CWrite Cycle Time Word Page15 nsPackaging96 Ball BGA
Mounting MethodSurface MountMemory InterfaceParallelMemory Organization128M x 16
Moisture Sensitivity Level3RoHS ComplianceCompliantREACH ComplianceREACH Unknown
QualificationJEDECECCNEAR99HTS Code8542.32.00.36

Overview of M15T2G16128A-BDBG2P – DDR3L SDRAM 2Gb 128Mbx16 800MHz DDR3(L)-1600 96 Ball BGA

The M15T2G16128A-BDBG2P is a 2Gb DDR3(L) SDRAM organized as 128M × 16 with an 8‑bank architecture optimized for high‑speed double‑data‑rate operation. It delivers DDR3(L)-1600 (800 MHz clock) performance in a compact 96‑ball BGA surface‑mount package.

Designed and qualified to JEDEC DDR3(L) specifications and offered in an industrial grade variant, this device is intended for general applications and industrial systems requiring a JEDEC‑compliant, RoHS‑compliant DDR3L memory solution with extended temperature capability.

Key Features

  • Memory Organization & Capacity — 2.147 Gbit total capacity, internally organized as 16M × 16 I/Os × 8 banks for efficient parallel access.
  • Performance — 800 MHz clock frequency supporting DDR3(L)-1600 data rate; access time specified at 13.75 ns and write cycle time (word page) at 15 ns.
  • DDR3(L) Architecture — 8n prefetch architecture with double‑data‑rate transfers on DQ/DQS/DM and source‑synchronous DQS pair timing.
  • Voltage & Interface — Supports SSTL_135 (VDD/VDDQ = 1.35V with specified tolerance) and SSTL_15 (VDD/VDDQ = 1.5V with specified tolerance); parallel memory interface.
  • Signal Integrity & Calibration — Differential clock (CK/CK) and data strobe (DQS/DQS); configurable drive strength (DS) and on‑die termination (RTT_Nom, RTT_WR); ZQ calibration via external ZQ pad (240 Ω ±1%).
  • Programmability & Timing Options — Wide CAS latency support (5–14), CAS write latency options, additive latency settings, selectable burst length/type, and multiple write recovery time settings for system tuning.
  • Power & Refresh Modes — Auto Refresh, Self Refresh, Partial Array Self Refresh (PASR) and Power Down modes to support power management strategies.
  • Package & Temperature Range — 96‑ball BGA, surface‑mount package; industrial operating temperature from −40°C to 95°C.
  • Standards & Compliance — JEDEC DDR3(L) compliant and RoHS‑compliant.

Typical Applications

  • Industrial Systems — Industrial‑grade temperature rating (−40°C to 95°C) and JEDEC qualification make this device suitable for industrial hardware where extended temperature operation is required.
  • General Applications — Designed for general applications requiring JEDEC‑compliant DDR3(L) memory and high‑speed double‑data‑rate performance.
  • High‑Speed Memory Interfaces — Differential clocking, DQS synchronization and on‑die termination features support robust high‑speed memory interface designs.

Unique Advantages

  • Flexible Voltage Operation — Supports both 1.35V and 1.5V SSTL operating points to accommodate system power budgets and compatibility needs.
  • Extensive Timing Options — Programmable CAS latencies, write latencies, additive latency and burst configuration provide designers granular control for timing optimization.
  • Signal Integrity Controls — Configurable drive strength and on‑die termination plus ZQ calibration (240 Ω ±1%) improve termination accuracy and signal stability at high data rates.
  • Industrial Temperature Range — Rated from −40°C to 95°C to support applications exposed to wide ambient temperature conditions.
  • JEDEC Compliance — Standards compliance helps maintain interoperability with DDR3(L) memory controller ecosystems and supports long‑term design stability.
  • Compact Surface‑Mount Package — 96‑ball BGA package enables dense board layouts and surface‑mount assembly processes.

Why Choose M15T2G16128A-BDBG2P?

The M15T2G16128A-BDBG2P provides a JEDEC‑compliant DDR3(L) memory solution that combines high‑speed DDR3(L)-1600 operation with industrial‑grade temperature capability and configurable signal integrity features. Its programmable timing options and dual voltage support allow system designers to tailor performance and power behavior to application requirements.

This device is well suited for designs and customers seeking a verified DDR3(L) memory component for general and industrial applications where DDR3 performance, JEDEC compatibility, and extended temperature operation are key selection criteria.

Request a quote or submit an inquiry to receive pricing, availability and lead‑time information for the M15T2G16128A-BDBG2P.

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