1ST110EN1F43E2LG

The Intel Stratix® 10 TX device 1ST110EN1F43E2LG is a high-performance field programmable gate array (FPGA) in a 1760-BBGA surface-mount package. Built on the Stratix® 10 TX architecture, it combines a monolithic 14 nm FPGA fabric with advanced transceiver tiles and on-package integration to address demanding bandwidth and compute requirements.

This device targets high-bandwidth system designs in data center, networking and communications markets, offering a balance of logic density, on-chip memory, high-speed I/O and hardened IP for connectivity and protocol offload.

Key Features

• Core Architecture  HyperFlex core architecture and 1,100,000 logic elements provide the fabric capacity required for large, performance-sensitive designs.
• High-speed Transceivers  Dual-mode transceivers capable of 57.8 Gbps PAM4 and 28.9 Gbps NRZ operation, supporting chip-to-chip, chip-to-module and backplane links.
• Hardened Protocol IP  Includes hardened PCI Express Gen3 and 10/25/100 Gbps Ethernet MAC IP blocks to reduce development time for common high-speed protocols.
• On-chip Memory and DSP  Total RAM capacity of 112,197,632 bits and hardened variable-precision DSP blocks enable complex buffering, packet processing and signal processing workloads.
• Embedded Processing (select devices)  Select Stratix 10 TX devices offer an embedded quad-core 64-bit Arm Cortex-A53 hard processor system (HPS) for application-class processing alongside programmable logic.
• I/O and Packaging  440 I/O pins in a 1760-BBGA (1760-FBGA, 42.5 × 42.5 mm) footprint, surface-mount package for dense board-level integration.
• Power and Supply  Core supply range specified at 820 mV to 880 mV for the device core domain.
• Operating Range and Grade  Extended grade device with an operating temperature range of 0 °C to 100 °C.
• Compliance  RoHS compliant.

Typical Applications

• Cloud and Data Center Networking  High aggregate bandwidth and hardened Ethernet/PCIe IP enable switching, routing and acceleration tasks in data center fabric and top-of-rack designs.
• Telecommunications and Optical Transport  Dual-mode high-speed transceivers support PAM4 and NRZ links for backplane, module and chip-to-chip optical and electrical interfaces.
• High-speed Packet Processing  Large logic capacity, abundant on-chip RAM and DSP resources allow implementation of packet classification, buffering and real-time processing pipelines.
• Compute Acceleration and Virtualization  Devices with an optional HPS provide a platform for offloading algorithmic workloads and extending hardware-assisted virtualization into programmable fabric.

Unique Advantages

• High Logic Density: 1,100,000 logic elements enable complex system-on-chip level designs without external ASICs.
• Flexible, High-speed I/O: Dual-mode transceivers supporting up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ provide design flexibility for a wide range of serial link standards.
• Protocol Offload with Hardened IP: Integrated PCIe Gen3 and 10/25/100 Gbps Ethernet MAC IP reduce development risk and accelerate time to market.
• Integrated Memory and DSP Resources: 112,197,632 bits of on-chip RAM and dedicated DSP blocks support buffering, encryption, FEC and signal-processing workloads.
• Compact, High-density Package: 1760-FBGA (42.5 × 42.5 mm) surface-mount package with 440 I/O enables space-efficient board designs.
• Designed for High-bandwidth Systems: Architecture and packaging combine to support multi-terabit aggregate bandwidth system requirements.

Why Choose 1ST110EN1F43E2LG?

The 1ST110EN1F43E2LG Stratix® 10 TX FPGA is positioned for designs that demand a combination of large programmable fabric, high-speed transceivers and hardened protocol IP. Its on-chip memory and DSP capabilities make it suitable for real-time packet processing, FEC, and signal-processing tasks while the optional embedded processor in select devices adds system-level flexibility.

For teams building scalable, high-bandwidth networking and compute accelerators, this device delivers a validated set of architectural features and package options that simplify integration and provide predictable, verifiable performance across the specified supply and temperature ranges.

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