1ST250EY2F55E1VG
| Part Description |
Stratix® 10 TX Field Programmable Gate Array (FPGA) IC 296 2500000 2912-BBGA, FCBGA |
|---|---|
| Quantity | 183 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 12 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 2912-FBGA, FC (55x55) | Grade | Extended | Operating Temperature | 0°C – 100°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 2912-BBGA, FCBGA | Number of I/O | 296 | Voltage | 770 mV - 970 mV | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 312500 | Number of Logic Elements/Cells | 2500000 | ||
| Number of Gates | N/A | ECCN | N/A | HTS Code | N/A | ||
| Qualification | N/A | Total RAM Bits | 204472320 |
Overview of 1ST250EY2F55E1VG – Stratix® 10 TX FPGA, 2912-FBGA (55×55)
The 1ST250EY2F55E1VG is an Intel Stratix® 10 TX Field Programmable Gate Array (FPGA) in a 2912-ball FCBGA package. It combines a high‑density FPGA fabric with Stratix 10 TX series innovations to address designs that require large logic capacity, extensive on-chip memory, and very high transceiver bandwidth.
Targeted at systems needing high aggregate bandwidth and integration, this device provides large-scale logic (2,500,000 logic elements), substantial embedded memory (204,472,320 total RAM bits), and up to 296 I/Os while operating across a 770 mV to 970 mV supply range and an extended 0 °C to 100 °C temperature window.
Key Features
- Core Architecture Intel Stratix 10 TX HyperFlex® core architecture is documented in the device family overview and delivers significantly increased core performance compared to prior generation Stratix devices.
- Logic Capacity 2,500,000 logic elements suitable for large, compute‑intensive FPGA designs.
- On‑Chip Memory 204,472,320 total RAM bits to support large buffering, packet processing, and on‑chip data storage.
- High‑Speed Transceivers Dual‑mode transceivers in Stratix 10 TX devices support up to 57.8 Gbps PAM4 and 28.9 Gbps NRZ operation for chip‑to‑chip, chip‑to‑module, and backplane links.
- Aggregate Bandwidth Capability Stratix 10 TX devices are described as capable of delivering over 8 Tbps of aggregate bandwidth across transceivers and fabric.
- Interfaces and Hardened IP Series documentation highlights hardened PCI Express Gen3 and multi‑rate Ethernet MAC IP blocks (10/25/100 Gbps) and Reed‑Solomon FEC support for NRZ and PAM4 signaling.
- Package and Mounting 2912‑ball FCBGA package (supplier package 2912‑FBGA, FC 55×55) designed for surface‑mount assembly.
- Electrical and Environmental Supply voltage range of 770 mV to 970 mV; operating temperature range 0 °C to 100 °C; RoHS compliant; grade: Extended.
Typical Applications
- High‑Bandwidth Networking Use the device's high‑speed transceivers and hardened Ethernet MAC IP to implement multi‑lane 10/25/100 Gbps links and FEC‑enabled packet processing.
- Backplane and Module Interfaces Dual‑mode transceiver support for PAM4 and NRZ makes the device suitable for chip‑to‑chip, chip‑to‑module, and backplane connectivity in system boards and line cards.
- PCIe‑Enabled Systems Leverage the documented hard PCI Express Gen3 IP to integrate high‑performance PCIe endpoints and bridges.
- Large‑Scale FPGA Designs High logic element count and abundant on‑chip RAM enable complex packet processing, protocol bridging, and hardware acceleration tasks.
Unique Advantages
- High Logic Density: 2,500,000 logic elements provide the capacity to implement large, parallel datapaths and deep processing pipelines.
- Massive On‑Chip Memory: 204,472,320 total RAM bits support large buffering, tables, and state storage without immediate external memory dependence.
- Versatile High‑Speed I/O: Dual‑mode transceivers (up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ) enable flexible integration across chip‑to‑chip, module, and backplane interfaces.
- Hardened Protocol IP: Built‑in support for PCIe Gen3 and multi‑rate Ethernet MAC IP reduces soft‑IP overhead and accelerates time‑to‑deployment.
- Package Integration: 2912‑ball FCBGA packaging (55×55) supports high pin density and surface mount assembly for compact system designs.
- Extended Operating Range: 0 °C to 100 °C operating range and RoHS compliance align with many commercial and enterprise design environments.
Why Choose 1ST250EY2F55E1VG?
The 1ST250EY2F55E1VG delivers the core Stratix 10 TX series capabilities—large logic capacity, substantial on‑chip memory, and high‑speed transceiver technology—packaged in a high‑density 2912‑ball FCBGA. It is positioned for designs that require significant logic and memory resources alongside multi‑terabit aggregate bandwidth and hardened protocol IP.
For teams building high‑bandwidth networking, PCIe‑enabled systems, or other data‑intensive applications, this device offers a scalable platform that aligns device‑level performance and on‑chip resources with system‑level bandwidth and integration needs.
Request a quote or submit a request for pricing and availability for the 1ST250EY2F55E1VG to receive detailed lead‑time and procurement information.

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