5SGSMD5H1F35C2N

IC FPGA 552 I/O 1152FBGA
Part Description

Stratix® V GS Field Programmable Gate Array (FPGA) IC 552 39936000 457000 1152-BBGA, FCBGA

Quantity 671 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerIntel
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package1152-FBGA (35x35)GradeCommercialOperating Temperature0°C – 85°C
Package / Case1152-BBGA, FCBGANumber of I/O552Voltage870 mV - 930 mV
Mounting MethodSurface MountRoHS ComplianceRoHS CompliantREACH ComplianceREACH Unknown
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs172600Number of Logic Elements/Cells457000
Number of GatesN/AECCN3A001A2CHTS Code8542.39.0001
QualificationN/ATotal RAM Bits39936000

Overview of 5SGSMD5H1F35C2N – Stratix V GS FPGA, 457,000 logic elements, 1152-FBGA (35×35)

The 5SGSMD5H1F35C2N is a Stratix® V GS field-programmable gate array (FPGA) in a 1152-FBGA (35×35) package. It delivers high logic capacity and on‑chip memory with an emphasis on transceiver-enabled, DSP‑centric applications across wireline, broadcast, and high‑performance computing markets. The device combines a large fabric, abundant DSP resources, and a high I/O count for designs that require dense, programmable logic and fast serial interfaces.

Key Features

  • Logic Capacity  Provides 457,000 logic elements for complex digital designs and large‑scale custom logic integration.
  • Embedded Memory  Approximately 39.94 Mbits of on‑chip RAM using 20 Kbit (M20K) memory blocks for buffering, packet queues, and intermediate storage.
  • DSP Resources  Stratix V GS devices include variable‑precision DSP blocks supporting up to 3,926 18×18 or 1,963 27×27 multipliers for high‑performance signal processing.
  • High‑Speed Serial I/O  Integrated transceivers with up to 14.1‑Gbps data‑rate capability (Stratix V GS family) and 552 general-purpose I/O pins to support dense board‑level connectivity.
  • Process & Fabric  Built on a 28‑nm process with redesigned adaptive logic modules (ALMs), fractional PLLs, and a comprehensive fabric clocking network for flexible timing architectures.
  • Power  Core supply range specified at 870 mV to 930 mV, enabling low‑voltage operation tailored to the Stratix V family’s power domains.
  • Package & Mounting  Surface‑mount 1152‑FBGA package (35×35) for high‑density board designs and thermal management considerations.
  • Operating Grade  Commercial operating temperature range of 0 °C to 85 °C.
  • Hard IP & Migration Path  Stratix V devices include an Embedded HardCopy Block and support a low‑risk, low‑cost path to HardCopy V ASICs for higher‑volume production.

Typical Applications

  • Transceiver‑based DSP Systems  High‑precision digital signal processing for broadcast, wireline, and communications equipment using the device’s variable‑precision DSP blocks and integrated transceivers.
  • High‑Bandwidth Networking  Packet processing and traffic management in 40G/100G network equipment where large logic capacity and on‑chip memory reduce external buffering needs.
  • Optical and Backplane Interfaces  Backplane and optical link interfaces that leverage the Stratix V GS transceiver capabilities and high I/O count for board‑level integration.
  • High‑Performance Computing  Compute‑intensive algorithms that benefit from dense logic, abundant DSP multipliers, and on‑chip memory for intermediate data storage.

Unique Advantages

  • High Logic Density:  457,000 logic elements accommodate large custom logic designs without immediate need for multiple devices.
  • Substantial On‑Chip Memory:  Approximately 39.94 Mbits of embedded memory lowers dependence on external DRAM for many buffering and queuing tasks.
  • DSP‑Centric Architecture:  Thousands of configurable multipliers enable efficient implementation of filters, transforms, and other signal‑processing kernels.
  • Extensive I/O and Transceivers:  552 I/O pins plus high‑speed transceivers support dense connectivity and high‑bandwidth serial links.
  • Low‑Voltage Core Operation:  870 mV to 930 mV core supply supports power‑sensitive system designs while aligning with Stratix V family voltage domains.
  • Production Scalability:  Embedded HardCopy Block and documented migration path to HardCopy V ASICs provide a clear route from prototyping to cost‑effective production.

Why Choose 5SGSMD5H1F35C2N?

This Stratix V GS FPGA is positioned for designers who need a balance of large programmable fabric, significant on‑chip memory, extensive DSP resources, and high I/O density in a surface‑mount FBGA package. It is well suited to transceiver‑enabled, DSP‑heavy applications where integration and performance are critical.

Choosing this device provides a clear design and production path within the Stratix V family, including architectural features and hard‑IP options that streamline migration to higher‑volume HardCopy V ASICs when required.

Request a quote or submit an inquiry to get pricing and availability for 5SGSMD5H1F35C2N and evaluate how this Stratix V GS FPGA fits your next high‑performance design.

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