EP20K160EBC356-1
| Part Description |
APEX-20KE® Field Programmable Gate Array (FPGA) IC 271 81920 6400 356-LBGA |
|---|---|
| Quantity | 968 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 356-BGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 356-LBGA | Number of I/O | 271 | Voltage | 1.71 V - 1.89 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 640 | Number of Logic Elements/Cells | 6400 | ||
| Number of Gates | 404000 | ECCN | 3A001A2A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 81920 |
Overview of EP20K160EBC356-1 – APEX-20KE® Field Programmable Gate Array (FPGA) IC 271 81920 6400 356-LBGA
The EP20K160EBC356-1 is a member of the APEX-20K family of FPGAs from Intel, delivering a mid-range, reprogrammable logic platform with integrated memory and flexible I/O. It combines a MultiCore architecture—including LUT logic, product-term logic and embedded memory blocks—with a compact 356-LBGA package to address designs that require moderate logic density, substantial on-chip RAM and a large number of I/O pins.
Typical use cases include embedded systems, interface bridging and prototyping where 6,400 logic elements, approximately 81,920 bits of embedded RAM and 271 I/O pins provide a balance of performance, integration and board-space efficiency. The device is RoHS compliant, surface-mount packaged and specified for commercial-grade operation.
Key Features
- Core logic — 6,400 logic elements (LEs) enabling register- and combinatorial-intensive functions within the APEX-20K MultiCore architecture.
- Embedded memory — Approximately 0.082 Mbits (81,920 bits) of on-chip RAM for FIFOs, dual-port RAM or CAM implementations using ESB resources.
- Logic capacity — Device-level capacity corresponding to 404,000 gates for system-level resource planning.
- I/O density — 271 user I/O pins to support broad peripheral interfacing and multi-signal connectivity on a single device.
- Clocking and timing — Benefits from APEX-20K family clock management features such as multiple PLLs, a low-skew clock tree and multiple global clocks for deterministic timing (family-level feature).
- MultiVolt I/O support — Series-level MultiVolt I/O capability facilitates interfacing with a range of voltage domains (1.8 V, 2.5 V, 3.3 V and 5.0 V as supported by the APEX-20K family).
- Power — Internal/primary supply specified at 1.71 V to 1.89 V for this device; family documentation highlights power-saving and low-power operation modes.
- Package and mounting — 356-LBGA (356-BGA, 35×35) surface-mount package for compact PCB implementations.
- Commercial temperature grade — Rated for 0 °C to 85 °C operation and specified as commercial grade.
- Regulatory — RoHS compliant.
Typical Applications
- Embedded controllers — Use the device’s 6,400 logic elements and on-chip memory to implement customized control logic, protocol handling and state machines for embedded applications.
- Interface bridging & protocol conversion — 271 I/O pins and MultiVolt I/O support allow the FPGA to bridge between different voltage domains and peripheral standards on a single board.
- Memory buffering and FIFO management — Approximately 81,920 bits of embedded RAM can be configured for FIFOs and buffering in data-path and streaming applications.
- Prototyping and development — The APEX-20K architecture provides flexible LUT and product-term logic resources for rapid prototyping of custom logic and mixed-signal interfaces.
Unique Advantages
- Balanced logic and memory integration: 6,400 logic elements plus 81,920 bits of embedded RAM reduce the need for discrete SRAM or FIFO components and simplify board-level design.
- High I/O count in a compact package: 271 I/O pins in a 356-LBGA (35×35) package deliver broad connectivity while minimizing PCB footprint.
- Flexible clock management: Family-level PLLs and low-skew clock architecture support complex clocking schemes for synchronous designs and multi-domain operation.
- Multi-domain interfacing: Series MultiVolt I/O support enables direct interfacing to multiple common voltage levels, easing integration with diverse peripherals.
- Commercial-grade reliability: Specified for 0 °C to 85 °C operation and RoHS compliant for standard commercial deployments.
- Surface-mount packaging: The 356-LBGA surface-mount form factor supports automated assembly and high-density board layouts.
Why Choose EP20K160EBC356-1?
The EP20K160EBC356-1 provides a practical combination of logic density, embedded memory and I/O connectivity within the proven APEX-20K family architecture. It is suited to engineers and designers who need a reprogrammable platform that balances on-chip resources and board-level integration for commercial applications.
Choose this FPGA when you require moderate gate capacity, substantial I/O and embedded RAM in a compact, RoHS-compliant LBGA package—backed by the APEX-20K family design features and Intel’s device documentation for development and integration.
Request a quote or submit a pricing inquiry to start integrating the EP20K160EBC356-1 into your next design.

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