EPF6016ATC144-2N

IC FPGA 117 I/O 144TQFP
Part Description

FLEX 6000 Field Programmable Gate Array (FPGA) IC 117 1320 144-LQFP

Quantity 727 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerIntel
Manufacturing StatusObsolete
Manufacturer Standard Lead TimeRFQ
Datasheet

Specifications & Environmental

Device Package144-TQFP (20x20)GradeCommercialOperating Temperature0°C – 85°C
Package / Case144-LQFPNumber of I/O117Voltage3 V - 3.6 V
Mounting MethodSurface MountRoHS ComplianceUnknownREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs132Number of Logic Elements/Cells1320
Number of Gates16000ECCN3A991DHTS Code8542.39.0001
QualificationN/A

Overview of EPF6016ATC144-2N – FLEX 6000 FPGA, 1,320 logic elements, 117 I/O, 144-LQFP

The EPF6016ATC144-2N is a FLEX 6000 family field-programmable gate array supplied in a 144-lead LQFP surface-mount package. Based on a register-rich, LUT-based OptiFLEX architecture, the device provides a reprogrammable SRAM-based implementation suitable for low-cost gate-array replacement, prototyping, and design testing.

With 1,320 logic elements, approximately 16,000 typical gates, and 117 usable I/O pins in the 144-pin package, the EPF6016ATC144-2N targets applications that require flexible I/O, in-circuit reconfiguration, and predictable routing and clocking in a commercial-grade temperature range.

Key Features

  • Architecture Register-rich, LUT-based OptiFLEX architecture that optimizes device area efficiency for reprogrammable logic.
  • Capacity 1,320 logic elements and approximately 16,000 typical gates for mid-density FPGA designs.
  • I/O and I/O Control 117 I/O pins in the 144-LQFP package with individual tri-state output enable control and programmable output slew-rate control to help manage switching noise and interface behavior.
  • Clocking and Interconnect Built-in low-skew clock distribution tree and FastTrack interconnect with dedicated carry and cascade chains for efficient arithmetic and wide-fan-in logic implementation.
  • System-level Flexibility In-circuit reconfigurability (ICR) via an external configuration device or intelligent controller and built-in IEEE Std. 1149.1-1990 JTAG boundary-scan test circuitry.
  • Power and Voltage Device supply range 3.0 V to 3.6 V. The FLEX 6000 family specifies low power consumption, with typical standby currents less than 0.5 mA.
  • Package and Mounting 144-LQFP surface-mount package (supplier device package: 144-TQFP 20×20) and commercial operating temperature from 0 °C to 85 °C.
  • Compliance RoHS compliant.
  • Test and Manufacture Devices are 100% functionally tested prior to shipment; JTAG BST is available without consuming additional device logic.

Typical Applications

  • Prototype and Development Reconfigurable FPGA logic enables rapid design iterations and in-system testing during prototype and evaluation phases.
  • Gate Array Replacement Low-cost programmable alternative to high-volume gate-array designs where post-production flexibility and fast design changes are required.
  • Mixed-Voltage Interface Bridging MultiVolt I/O support allows the device to bridge between systems operating at different I/O voltages.
  • Control and Signal Glue Logic Implement custom control, glue logic, and arithmetic functions using dedicated carry and cascade chains and the device’s logic element resources.

Unique Advantages

  • Reprogrammable Flexibility: SRAM-based configuration and in-circuit reconfigurability let designers update functionality without replacing hardware.
  • Verified Quality: 100% functional testing prior to shipment reduces verification overhead during production integration.
  • Predictable Timing and Arithmetic Support: Low-skew clock distribution, FastTrack interconnect, and dedicated carry/cascade chains simplify implementation of timing-critical and arithmetic functions.
  • Flexible I/O Control: Individual tri-state enables and programmable slew-rate control help manage signal integrity across diverse interfaces.
  • Compact, Surface-Mount Package: 144-LQFP packaging and surface-mount mounting simplify PCB layout for space-constrained boards.

Why Choose EPF6016ATC144-2N?

The EPF6016ATC144-2N offers a mid-density, reprogrammable FPGA option combining 1,320 logic elements, approximately 16,000 typical gates, and 117 I/O pins in a 144-LQFP surface-mount package. Its OptiFLEX architecture, dedicated arithmetic chains, and built-in clock distribution provide a practical balance of capacity, predictable routing, and system-level flexibility for design teams focused on prototyping, gate-array replacement, and board-level logic integration.

With support for in-circuit reconfiguration, JTAG boundary-scan, and low standby power, this device is well suited for commercial designs that require reconfigurability, iterative development, and straightforward board-level integration, while maintaining RoHS compliance and standard commercial temperature operation.

Request a quote or contact our sales team to check availability, lead times, and pricing for the EPF6016ATC144-2N.

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