EPF6024ATI144-3
| Part Description |
FLEX 6000 Field Programmable Gate Array (FPGA) IC 117 1960 144-LQFP |
|---|---|
| Quantity | 1,984 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 144-TQFP (20x20) | Grade | Industrial | Operating Temperature | -40°C – 100°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 144-LQFP | Number of I/O | 117 | Voltage | 3 V - 3.6 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unknown | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 196 | Number of Logic Elements/Cells | 1960 | ||
| Number of Gates | 24000 | ECCN | OBSOLETE | HTS Code | 0000.00.0000 | ||
| Qualification | N/A |
Overview of EPF6024ATI144-3 – FLEX 6000 FPGA, 117 I/O, 1960 logic elements, 144‑LQFP
The EPF6024ATI144-3 is a FLEX 6000 family field-programmable gate array (FPGA) supplied in a 144‑pin LQFP surface-mount package. It combines a register-rich, look-up table (LUT)-based architecture with the OptiFLEX area-efficiency approach to deliver up to 24,000 typical gates and 1,960 logic elements in a compact footprint.
Designed for low-cost gate-array replacement, prototyping and in-circuit reconfigurable designs, this device targets applications that require dense user logic, flexible I/O, and robust production testability across an industrial temperature range.
Key Features
- Core architecture Register-rich, LUT-based OptiFLEX architecture providing approximately 24,000 typical gates and 1,960 logic elements for compact, reprogrammable logic implementations.
- Logic and routing FastTrack interconnect structure with dedicated carry and cascade chains to support arithmetic functions and high-fan-in logic structures.
- I/O capability 117 user I/O pins with individual tri-state output enable control and programmable output slew-rate to manage switching noise and interface timing.
- Configuration and in-system flexibility Reconfigurable SRAM-based device with support for in-circuit reconfigurability (ICR) via external configuration device or intelligent controller.
- Clock and timing Built-in low-skew clock distribution tree and four low-skew global paths for clock, clear, preset, or other global signals.
- Test and diagnostics IEEE Std. 1149.1 JTAG boundary-scan (BST) circuitry included and 100% functional testing at shipment for production readiness.
- Package and mounting Surface-mount 144‑LQFP package (supplier device package listed as 144‑TQFP 20×20) for compact board-level integration.
- Power and temperature Supply voltage range 3.0 V to 3.6 V and industrial operating temperature range of −40 °C to 100 °C.
- Environmental compliance RoHS compliant.
Typical Applications
- Gate‑array replacement and custom ASIC prototyping — Low-cost programmable alternative to high-volume gate arrays, enabling fast design changes during prototyping and testing.
- In-circuit reconfigurable systems — On-board reconfiguration via external configuration device or controller to update logic without board swaps.
- Multi‑domain interface bridging — Flexible I/O and programmable slew control help adapt the device as a bridge between different voltage or signaling domains.
- High‑density control and glue logic — 1,960 logic elements and 117 I/O pins provide capacity for compact control, decoding, and glue logic functions on space-constrained PCBs.
Unique Advantages
- Flexible, reprogrammable platform: SRAM-based configuration and in-circuit reconfigurability let you iterate designs quickly without respins.
- High logic density: Approximately 24,000 typical gates and 1,960 logic elements enable substantial custom logic in a small package.
- Robust I/O control: 117 I/O pins with per-pin tri-state enable and programmable slew-rate simplify board-level interfacing and signal integrity management.
- Production-ready testability: Built-in IEEE 1149.1 JTAG boundary-scan and 100% functional device testing support reliable manufacturing and debug.
- Industrial temperature range: Rated for −40 °C to 100 °C to meet a wide range of operating environments.
- Compact surface-mount package: 144‑pin LQFP (TQFP 20×20 footprint) supports dense board integration while maintaining pin compatibility within the FLEX 6000 family.
Why Choose EPF6024ATI144-3?
The EPF6024ATI144-3 positions itself as a practical, reprogrammable alternative to fixed gate-array solutions where design agility, I/O flexibility, and production testability matter. With optical area-efficiency from the OptiFLEX architecture, a substantial logic resource set, and industry-grade temperature capability, this device is suited to engineering teams that need to iterate quickly, consolidate glue logic, or implement custom control functions in a compact form factor.
Supported by the FLEX 6000 family design flow and production-level test features, the EPF6024ATI144-3 offers a balanced combination of density, configurability, and board-level integration for mid-density FPGA applications.
Request a quote or submit a pricing inquiry for EPF6024ATI144-3 to evaluate fit for your next design or production run.

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