LAE3-35EA-6FN672E
| Part Description |
LA-ECP3 Field Programmable Gate Array (FPGA) IC 310 1358848 33000 672-BBGA |
|---|---|
| Quantity | 505 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Lattice Semiconductor Corporation |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 20 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FPBGA (27x27) | Grade | Automotive | Operating Temperature | -40°C – 125°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 310 | Voltage | 1.14 V - 1.26 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | ROHS3 Compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 4125 | Number of Logic Elements/Cells | 33000 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | AEC-Q100 | Total RAM Bits | 1358848 |
Overview of LAE3-35EA-6FN672E – LA-ECP3 Automotive FPGA, 33,000 logic elements, 310 I/Os
The LAE3-35EA-6FN672E is an automotive-grade Field Programmable Gate Array (FPGA) from the LA‑LatticeECP3 family. It delivers a fabric optimized for high integration with 33,000 logic elements, extensive I/O, on-chip embedded memory and DSP resources suited for high-performance embedded and automotive electronics.
This device targets designs that require dense logic, high-speed serial interfaces and reliable operation across automotive temperature and qualification ranges, providing a compact 672-ball BGA package with AEC‑Q100 qualification and RoHS compliance.
Key Features
- Logic Density – 33,000 logic elements providing substantial LUT-based logic capacity for complex system integration.
- Embedded Memory – Approximately 1.36 Mbits of on-chip embedded RAM (1,358,848 bits) for frame buffering, state machines and intermediate data storage.
- I/O Capacity – 310 user I/Os with programmable sysI/O buffer support for a wide range of parallel and differential signaling standards.
- High-Speed SERDES – Family-level SERDES capabilities supporting 150 Mbps to 3.2 Gbps and multi-protocol operation (e.g., PCI Express, Ethernet, CPRI), enabling high-throughput serial links.
- sysDSP – Enhanced DSP slice architecture (family feature) with cascaded slices and wide ALU support for high-performance multiply-accumulate operations and signal processing tasks.
- Clocking Resources – Multiple PLLs and DLLs (family-level) to support flexible clocking and timing architectures for synchronous systems.
- Configuration & Reliability – Flexible configuration with SPI boot support, dual-boot images and soft error detection features (family-level configuration options).
- Package & Mounting – 672‑BBGA (672‑FPBGA, 27 × 27 mm) surface-mount package for compact board integration.
- Power & Temperature – Core supply range 1.14 V to 1.26 V and qualified operating temperature range of −40°C to 125°C for automotive environments.
- Automotive Qualification & Compliance – AEC‑Q100 qualification and RoHS compliance for use in automotive designs.
Typical Applications
- Automotive Networking & Gateway – High I/O count and SERDES support enable bridge and aggregation functions between in-vehicle high-speed serial links and parallel interfaces.
- Advanced Signal Processing – DSP slice resources and substantial embedded RAM support filtering, sensor data fusion and real-time processing tasks.
- High-Speed Serial Communications – SERDES channels and protocol support are suited for applications implementing PCIe, Ethernet variants and other multi-gigabit links.
- Infotainment & Telematics – Large I/O set, on-chip memory and configurable logic allow integration of display, audio and network interfaces in compact modules.
Unique Advantages
- Automotive-Qualified Reliability: AEC‑Q100 qualification and a −40°C to 125°C operating range support deployment in automotive environments.
- High Integration Density: 33,000 logic elements combined with on-chip memory reduce external components and simplify PCB routing.
- Flexible High-Speed Connectivity: SERDES and programmable sysI/O buffers enable multi‑protocol serial links and a broad set of I/O standards on the same device.
- Dedicated DSP Resources: sysDSP architecture (family feature) provides multiply-accumulate and wide-ALU capabilities for compute-intensive signal tasks.
- Compact, Robust Packaging: 672‑BBGA (27 × 27 mm) surface-mount package offers a high-pin-count, space-efficient footprint for complex systems.
- Controlled Power Domain: Narrow core voltage range (1.14 V–1.26 V) simplifies power-supply design for the core domain.
Why Choose LAE3-35EA-6FN672E?
The LAE3-35EA-6FN672E positions itself as a robust, automotive-qualified FPGA option combining substantial logic capacity, embedded memory and versatile I/O in a compact BGA package. It is well suited for engineers building automotive networking, signal processing and high-speed interface designs that require a qualified, high-density programmable device.
Choosing this LA‑ECP3 device gives designers a path to consolidate functionality, reduce external components and leverage family-level features such as high-speed SERDES, enhanced DSP slices and flexible configuration options for scalable, long-term platform development.
Request a quote or submit an inquiry for LAE3-35EA-6FN672E to discuss availability, pricing and lead time for your project needs.

Date Founded: 1983
Headquarters: Hillsboro, Oregon, USA
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