LFE2M50SE-6FN672C

IC FPGA 372 I/O 672FPBGA
Part Description

ECP2M Field Programmable Gate Array (FPGA) IC 372 4246528 48000 672-BBGA

Quantity 733 Available (as of May 5, 2026)
Product CategoryField Programmable Gate Array (FPGA)
ManufacturerLattice Semiconductor Corporation
Manufacturing StatusActive
Manufacturer Standard Lead Time20 Weeks
Datasheet

Specifications & Environmental

Device Package672-FPBGA (27x27)GradeCommercialOperating Temperature0°C – 85°C
Package / Case672-BBGANumber of I/O372Voltage1.14 V - 1.26 V
Mounting MethodSurface MountRoHS ComplianceROHS3 CompliantREACH ComplianceREACH Unaffected
Moisture Sensitivity Level3 (168 Hours)Number of LABs/CLBs6000Number of Logic Elements/Cells48000
Number of GatesN/AECCN3A991DHTS Code8542.39.0001
QualificationN/ATotal RAM Bits4246528

Overview of LFE2M50SE-6FN672C – ECP2M FPGA, approximately 48,000 logic elements, 672-BBGA

The LFE2M50SE-6FN672C is a Lattice Semiconductor ECP2M family Field Programmable Gate Array (FPGA) delivered in a 672-ball BGA package. It integrates approximately 48,000 logic elements, a high I/O count (372 pins), and approximately 4.25 Mbits of embedded RAM to address demanding system integration tasks.

Built for applications that require a mix of programmable logic, DSP acceleration and high-speed serial connectivity, this commercial-grade device offers on-chip clocking, advanced I/O support and SERDES capability as defined for the LatticeECP2/M family.

Key Features

  • Logic Capacity  Approximately 48,000 logic elements provide substantial combinational and sequential resources for complex FPGA designs.
  • Embedded Memory  Approximately 4.25 Mbits of on-chip RAM (total RAM bits: 4,246,528) for FIFOs, buffering and local data storage.
  • High I/O Count  372 user I/O pins support wide external connectivity and complex board-level interfacing.
  • sysDSP Blocks  Family-level sysDSP blocks provide dedicated multiply-accumulate capability for signal processing and algorithm acceleration.
  • Embedded SERDES  LatticeECP2M family SERDES support high-speed serial links (data rates from 250 Mbps to 3.125 Gbps) for serial protocols and backplane or chip-to-chip interfaces.
  • Clocking Resources  On-chip PLLs and DLLs (family supports general-purpose and system PLL/DLL structures) for flexible clock multiplication, division and phase adjustment.
  • Flexible I/O Standards  Programmable I/O buffer support across a wide range of single-ended and differential standards (family-level detail) to match diverse interface requirements.
  • Configuration and Security  Family features include SPI boot flash interface, dual boot images and optional bitstream encryption on “S” versions.
  • Package & Mounting  672-ball BGA (supplier package: 672-FPBGA, 27×27 mm) surface-mount package for compact board footprint and high-density routing.
  • Power & Operating Range  Core supply range 1.14 V to 1.26 V; commercial operating temperature range 0 °C to 85 °C. RoHS compliant.

Typical Applications

  • High-Speed Serial Communications  Implement PCI Express, Ethernet and other serial protocols using the device’s SERDES and programmable I/O.
  • Signal Processing & DSP Acceleration  Offload filtering, FFTs, and arithmetic-heavy tasks to on-chip sysDSP blocks and embedded RAM.
  • Memory Interface & Buffering  Use embedded RAM and dedicated DDR support at the family level for memory controllers, buffering and data path staging.
  • System Integration & Glue Logic  High logic capacity and 372 I/Os make the device suitable for consolidating multiple functions and implementing complex board-level control.

Unique Advantages

  • Substantial On-Chip Resources:  Approximately 48,000 logic elements and several Mbits of embedded RAM reduce external component count and simplify system design.
  • High I/O Density:  372 I/Os enable broad peripheral connectivity and multi-channel interfacing without additional IO expanders.
  • Serial Link Capability:  Family SERDES support for 250 Mbps–3.125 Gbps links enables integration of contemporary high-speed protocols.
  • Dedicated DSP Support:  sysDSP blocks accelerate arithmetic workloads, improving processing throughput for real-time signal tasks.
  • Compact, Board-Friendly Package:  672-ball BGA (27×27 mm) offers a high-density, surface-mount solution for space-constrained designs.
  • Commercial-Grade Availability:  Specified for 0 °C to 85 °C operation with RoHS compliance for standard commercial applications.

Why Choose LFE2M50SE-6FN672C?

The LFE2M50SE-6FN672C combines a large programmable fabric, ample embedded memory and a high pin count in a compact 672-ball BGA package—making it well suited for communication, networking and DSP-centric embedded systems that need on-chip integration and flexible I/O. Family-level features such as embedded SERDES, dedicated DSP blocks and robust clocking resources provide a balanced platform for designs that require both logic density and high-speed connectivity.

This device is appropriate for engineers and teams looking to consolidate multiple discrete functions into a single programmable IC, reduce BOM complexity, and leverage Lattice ECP2M family capabilities in commercial-temperature designs.

Request a quote or submit a pricing and availability inquiry to receive lead-time and ordering information for the LFE2M50SE-6FN672C.

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