LFE3-35EA-9FN672C

The LFE3-35EA-9FN672C is a field programmable gate array (FPGA) IC from Lattice Semiconductor Corporation based on the LatticeECP3 family architecture. It combines a mid-range logic fabric with integrated DSP resources, flexible high-speed I/O and embedded memory to address mid-density, high-throughput embedded designs.

Targeted at applications that require serial connectivity, signal processing and memory interfacing, this commercial-grade, surface-mount device delivers system-level integration while maintaining a compact 672-BBGA (27 × 27 mm) package and a low-voltage 1.14 V to 1.26 V core supply range.

Key Features

• Core Logic  33,000 logic elements provide the programmable fabric for glue logic, protocol processing and custom datapath implementations.
• Embedded Memory  Approximately 1.36 Mbits of on-chip RAM (1,358,848 bits) for buffers, FIFOs and on-chip data storage.
• Enhanced DSP Capability  sysDSP architecture from the ECP3 family provides cascadable multiply-accumulate resources and advanced ALU operations suitable for real-time signal processing and high‑throughput arithmetic tasks.
• High-speed Serial (SERDES)  Embedded SERDES technology supports data rates from 150 Mbps to 3.2 Gbps and common protocols such as PCI Express, SONET/SDH, Ethernet, CPRI, SMPTE 3G and Serial RapidIO for high-bandwidth links.
• Extensive I/O Support  Up to 310 user I/Os with programmable sysI/O buffer options and support for standards including LVTTL, LVCMOS, SSTL, HSTL, LVDS and others for flexible interface design.
• Clocking and Timing  Family-level sysCLOCK support includes PLLs and DLLs for robust clocking and source-synchronous interfaces (DDR support and dedicated read/write leveling functionality highlighted in the ECP3 family datasheet).
• Package, Power and Grade  672-FPBGA (27 × 27 mm) surface-mount package; commercial grade with operating temperature 0 °C to 85 °C and a core voltage supply range of 1.14 V to 1.26 V.
• Compliance  RoHS compliant.

Typical Applications

• Networking & Communications  Implement protocol engines, packet processing and high-speed serial links using integrated SERDES and flexible I/O standards for Ethernet, PCIe and telecom interfaces.
• Video & Broadcast Systems  Support SMPTE 3G and other broadcast-grade serial interfaces while providing on-chip buffering and DSP resources for real-time video data handling.
• High-speed Data Acquisition and DSP  Use sysDSP resources and ADC/DAC interface support for front-end signal conditioning, filtering and real-time analysis in measurement and instrumentation applications.
• Memory Interface and Controller Logic  Implement DDR/DDR2/DDR3 interface logic, buffering and custom memory controllers leveraging source-synchronous I/O and on-chip RAM.

Unique Advantages

• Balanced integration of logic and memory: 33,000 logic elements paired with ~1.36 Mbits of embedded RAM reduce external memory needs and simplify board-level design.
• Broad serial protocol support: SERDES capability covering 150 Mbps–3.2 Gbps enables implementation of multiple high-speed link standards within a single device.
• Flexible I/O standards: Up to 310 user I/Os with programmable buffer types accommodate diverse peripheral and memory interfaces without major hardware changes.
• DSP-oriented architecture: sysDSP features facilitate compact, efficient implementations of multiply-accumulate and other compute-intensive functions.
• Compact production-ready package: 672‑BBGA (27 × 27 mm) surface-mount package and commercial temperature rating support volume assembly and deployment in commercial systems.
• Regulatory and environmental readiness: RoHS compliance supports environmental and manufacturing requirements.

Why Choose LFE3-35EA-9FN672C?

The LFE3-35EA-9FN672C delivers a practical combination of mid-range programmable logic, embedded memory and DSP/serial interface capability within a compact 672-BBGA package. It is well suited to engineers designing communications, video, data acquisition and memory-interface subsystems who need a balance of throughput, integration and on-chip resources.

As a member of the LatticeECP3 family, the device benefits from architecture-level features such as sysDSP, flexible sysI/O and embedded SERDES, offering a scalable platform for mid-density FPGA designs where system integration and interface diversity matter.

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