XCV150-6BG352C
| Part Description |
Virtex® Field Programmable Gate Array (FPGA) IC 260 49152 3888 352-LBGA Exposed Pad, Metal |
|---|---|
| Quantity | 1,210 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | AMD |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 352-MBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 352-LBGA Exposed Pad, Metal | Number of I/O | 260 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 864 | Number of Logic Elements/Cells | 3888 | ||
| Number of Gates | 164674 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 49152 |
Overview of XCV150-6BG352C – Virtex® Field Programmable Gate Array (FPGA) IC, 3,888 logic elements
The XCV150-6BG352C is an SRAM-based Virtex® FPGA offering high-density, reprogrammable logic in a 352-LBGA exposed pad metal package. The device integrates 3,888 logic elements, 49,152 bits of on-chip RAM, and 260 user I/Os to support complex, reconfigurable digital designs.
Designed for high-performance, high-capacity programmable logic applications, this device provides clock management, multi-standard I/O support and flexible memory options to accelerate system integration and shorten design time.
Key Features
- Core capacity — 3,888 logic elements and approximately 164,674 system gates provide a balance of density and routing resources for medium-complexity designs.
- On-chip memory — 49,152 total RAM bits with LUTs configurable as 16-bit/32-bit RAM, dual-ported RAM options and dedicated 4k-bit RAM blocks for flexible data buffering and state storage.
- I/O and interface support — 260 user I/Os with Multi-standard SelectIO™ interfaces supporting multiple high-performance interface standards; device-level support for 66-MHz PCI compliance and hot-swap for Compact PCI.
- Clock management — Four dedicated delay-locked loops (DLLs), four primary low-skew global clock nets and 24 secondary local clock nets enable advanced clock control and distribution.
- Architecture for arithmetic and wide functions — Dedicated carry logic, multiplier support and cascade chains facilitate high-speed arithmetic and wide-input logic implementations.
- Configuration and re-programmability — SRAM-based in-system configuration with unlimited re-programmability and four programming modes for flexible deployment and iterative development.
- Package and power — Surface-mount 352-LBGA exposed pad metal package (352-MBGA, 35×35); rated supply voltage 2.375 V to 2.625 V and commercial operating temperature range 0 °C to 85 °C.
- Manufacturing and test — 0.22 μm 5-layer metal CMOS process and 100% factory tested for production consistency; RoHS compliant.
- System and design support — Supported by FPGA Foundation™ and Alliance development systems for design implementation and toolchain integration.
Typical Applications
- PCI-based systems — Integration into 66-MHz PCI designs where a reprogrammable logic device provides protocol bridging, custom logic or peripheral control.
- Compact PCI modules — Hot-swappable Compact PCI modules that require field reprogrammability and high I/O density.
- Custom data-path and signal processing — Implement arithmetic engines, custom datapaths and buffering using dedicated carry/multiplier logic and on-chip RAM.
- Prototyping and reconfigurable logic — Replace mask-programmed gate arrays for iterative design cycles and in-system updates using SRAM-based configuration.
Unique Advantages
- High-density programmable logic: 3,888 logic elements and ~164,674 gates enable medium-complexity designs without external glue logic.
- Flexible embedded memory: 49,152 bits of on-chip RAM with configurable LUT-based RAM and dual-ported blocks simplifies data buffering and control state implementation.
- Extensive I/O and protocol support: 260 user I/Os with SelectIO™ capabilities support diverse interface standards and direct connections to external memory devices.
- Robust clock control: Four DLLs and multiple clock nets provide low-skew distribution and advanced timing management for synchronous systems.
- Field re-programmability: SRAM-based configuration with multiple programming modes enables in-system updates and design iteration without device replacement.
- Production-ready package: Surface-mount 352-LBGA exposed pad metal package with RoHS compliance and full factory test coverage eases assembly and qualification for commercial products.
Why Choose XCV150-6BG352C?
The XCV150-6BG352C positions itself as a versatile, mid-density Virtex® FPGA tailored for designs that need a balance of logic capacity, on-chip memory and I/O density in a compact surface-mount package. Its SRAM-based architecture and multiple configuration modes support iterative development and in-field updates, while built-in clock management and dedicated arithmetic resources help implement high-performance data paths.
This device is well suited for engineering teams building PCI or Compact PCI modules, prototype systems replacing mask-programmed logic, and other commercial applications where reconfigurable logic, predictable supply voltage range (2.375 V–2.625 V) and a commercial temperature rating (0 °C–85 °C) are required. The combination of manufacturing test coverage and available development support aims to reduce integration risk and speed time-to-market.
Request a quote or submit an inquiry for pricing and availability of the XCV150-6BG352C to move your design toward production-ready programmable logic.

Date Founded: 1969
Headquarters: Santa Clara, California, USA
Employees: 25,000+
Revenue: $22.68 Billion
Certifications and Memberships: ISO9001:2015, RoHS, REACH








