NG80960JD3V50

The NG80960JD3V50 is a single‑core, 32‑bit i960 microprocessor in a 132‑lead PQFP surface‑mount package. It is specified at 50 MHz core speed and targets embedded system designs that require on‑chip memory resources, cache, and flexible bus configuration.

Built for commercial‑grade applications, the device operates from a 3.3 V supply, offers 5 V tolerant inputs with TTL‑compatible outputs, and includes integrated DRAM controller support to simplify system memory interfacing.

Key Features

• Core and Architecture  i960 architecture, single 32‑bit core with one‑instruction‑per‑clock execution for predictable instruction throughput.
• Clock and Performance  Specified at 50 MHz core speed; JD variant characteristics include cache and on‑chip resources that improve code and data access latency.
• Cache and On‑Chip Memory  Includes a 4 KB two‑way set‑associative instruction cache and a 2 KB direct mapped data cache (JD variant), plus 1 KB on‑chip data RAM for critical variable storage and single‑cycle access.
• Memory and Bus  High‑bandwidth burst bus with 32‑bit multiplexed address/data capability and selectable 8/16/32‑bit bus widths; supports unaligned accesses and both big‑ and little‑endian byte ordering.
• Timers and Interrupts  Two on‑chip 32‑bit timers with prescaling (1, 2, 4, 8) and a high‑speed interrupt controller offering multiple programmable priorities and maskable pins plus NMI# support.
• Power and I/O  3.3 V supply, 5 V tolerant inputs and TTL‑compatible outputs; includes a halt mode for low power operation.
• Package and Mounting  132‑lead plastic quad flat pack (132‑PQFP) package, 24.13 × 24.13 mm footprint, surface mount.
• Environmental and Grade  Commercial grade device with operating temperature range 0 °C to 100 °C and RoHS compliant status.
• Debug and Test  IEEE 1149.1 (JTAG) boundary‑scan compatibility for structural test and debug.

Typical Applications

• Embedded Control Systems  Single‑core 32‑bit processing with on‑chip caches and timers suited to general embedded control and processing tasks.
• DRAM‑based System Designs  Integrated DRAM controller support and flexible bus widths simplify interfacing to external memory subsystems.
• Commercial Electronics  Commercial temperature range and surface‑mount PQFP packaging make the device suitable for a variety of commercial embedded products.
• Compact Surface‑Mount Modules  132‑PQFP footprint (24.13 × 24.13 mm) supports high‑density, surface‑mount PCB designs.

Unique Advantages

• Predictable Instruction Throughput: One‑instruction‑per‑clock execution of the i960 core enables deterministic code performance for timing‑sensitive tasks.
• Integrated Cache and RAM: On‑chip instruction and data caches plus 1 KB internal data RAM reduce external memory accesses and improve response for critical variables.
• Flexible Memory Interface: Selectable bus widths and high‑bandwidth burst bus simplify integration with a range of external memory configurations, including DRAM.
• Robust I/O Levels: 3.3 V operation with 5 V tolerant inputs and TTL‑compatible outputs eases interfacing with mixed‑voltage logic on commercial PCBs.
• On‑Chip Timers and Interrupts: Two 32‑bit timers and a programmable interrupt controller provide fine‑grained control and priority handling for embedded event management.
• Test and Debug Support: JTAG boundary‑scan compatibility assists structural testing and system debug during development and manufacturing.

Why Choose NG80960JD3V50?

The NG80960JD3V50 combines the i960 single‑core 32‑bit architecture with on‑chip caches, data RAM, timers, and a flexible bus interface to deliver a compact, integrated microprocessor solution for commercial embedded designs. Its 3.3 V operation with 5 V tolerant inputs and PQFP surface‑mount packaging make it straightforward to integrate on modern PCB layouts.

This device suits teams building commercial‑grade embedded systems that require deterministic instruction execution, integrated memory resources, and standard test/debug support. The combination of cache, on‑chip RAM, and DRAM controller capability supports designs that need improved code/data locality while retaining configurable external memory options.

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