EP1K10FC256-2N
| Part Description |
ACEX-1K® Field Programmable Gate Array (FPGA) IC 136 12288 576 256-BGA |
|---|---|
| Quantity | 435 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 14 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 256-FBGA (17x17) | Grade | Commercial | Operating Temperature | 0°C – 70°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 256-BGA | Number of I/O | 136 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 72 | Number of Logic Elements/Cells | 576 | ||
| Number of Gates | 56000 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 12288 |
Overview of EP1K10FC256-2N – ACEX-1K® Field Programmable Gate Array (FPGA) IC 136 12288 576 256-BGA
The EP1K10FC256-2N is an ACEX-1K family field programmable gate array from Intel. It combines a logic array and embedded memory blocks to deliver a compact, reconfigurable solution for system-on-a-programmable-chip (SOPC) integration and medium-density logic tasks.
With 576 logic elements, approximately 12,288 bits of embedded RAM, and 136 user I/O pins in a 256-FBGA (17×17) package, this commercial-grade device is targeted at communications, control, and general-purpose programmable logic applications that require reconfigurability and integrated memory resources.
Key Features
- Logic Capacity Provides 576 logic elements and a typical gate count of 56,000, suitable for medium-density digital designs.
- Embedded Memory (EABs) Approximately 12,288 bits of total on-chip RAM with embedded array blocks that support dual-port capability and up to 16-bit width per block for efficient megafunction and memory implementation.
- I/O and Interfacing 136 user I/O pins with programmable I/O options including individual tri-state control, open-drain capability, programmable output slew-rate, and clamp-to-VCCIO selection on a per-pin basis.
- Clocking and Timing Built-in low-skew clock distribution trees with support for multiple global clock and clear signals; ClockLock™ and ClockBoost™ options are available in the ACEX-1K family to reduce clock delay and skew.
- Configuration and Test In-circuit reconfigurability via external configuration devices, intelligent controller, or JTAG; includes built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 as part of the family feature set.
- Power and Voltage Operates with an internal 2.5 V supply; specified external supply range is 2.375 V to 2.625 V.
- Package & Mounting 256-ball FineLine BGA (256-FBGA, 17×17) package, surface-mount mounting for compact board integration.
- Operating Conditions & Compliance Commercial grade operation from 0 °C to 70 °C; RoHS compliant.
Typical Applications
- Communications Equipment Implement protocol bridging, packet buffering, or control logic using embedded RAM and reconfigurable logic.
- SOPC and Embedded Functions Integrate megafunctions and custom logic into a single device using EABs for efficient memory and specialized logic functions.
- Peripheral and Interface Control Leverage 136 user I/Os and programmable I/O features for interfacing with mixed-voltage peripherals and system-level glue logic.
- Prototyping and Reconfigurable Systems Use in designs that benefit from in-circuit reconfigurability and JTAG-based boundary-scan testability.
Unique Advantages
- Integrated Embedded RAM EAB blocks provide dual-port memory with up to 16-bit widths, enabling compact implementation of buffers and state storage without external memory.
- Flexible I/O Options Per-pin tri-state control, open-drain capability, and slew-rate programming help tailor signaling and reduce board-level complexity.
- Reconfigurability and Testability In-circuit reconfigurability and built-in JTAG boundary-scan allow design iteration and board-level testing without consuming user logic.
- Clocking Features Family-level support for low-skew clock distribution and ClockLock/ClockBoost options helps manage timing across distributed logic functions.
- Compact Surface-Mount Package 256-FBGA (17×17) provides a high pin-count, compact footprint suitable for space-constrained PCBs.
- Compliance and Environmental RoHS compliance supports deployment in modern assembly flows and regulatory environments.
Why Choose EP1K10FC256-2N?
The EP1K10FC256-2N positions itself as a medium-density, commercially graded FPGA offering a balanced mix of logic elements, embedded RAM, and I/O in a compact 256-FBGA package. It is well suited to designers who need on-chip memory resources and flexible I/O options for communications, control, or embedded system functions.
As part of the ACEX-1K family, this device benefits from family-level architecture and design support, enabling straightforward migration within the series and access to established development tool flows referenced in the ACEX-1K documentation.
Request a quote or submit an inquiry to receive pricing and availability information for the EP1K10FC256-2N and to discuss how it fits your next design.

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