EP1SGX10DF672C7N
| Part Description |
Stratix® GX Field Programmable Gate Array (FPGA) IC 362 920448 10570 672-BBGA |
|---|---|
| Quantity | 971 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FBGA (27x27) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 362 | Voltage | 1.425 V - 1.575 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | Unknown | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1057 | Number of Logic Elements/Cells | 10570 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 920448 |
Overview of EP1SGX10DF672C7N – Stratix® GX Field Programmable Gate Array (FPGA) IC 362 920448 10570 672-BBGA
The EP1SGX10DF672C7N is a Stratix® GX family FPGA in a 672-ball FineLine BGA package targeted at commercial electronic designs. It combines a high-performance 1.5‑V logic array architecture with on-chip embedded memory and extensive I/O to address high-speed backplane, chip-to-chip, and communications protocol-bridging applications.
Key device-level specifications include 10,570 logic elements, approximately 0.92 Mbits of embedded RAM, 362 I/O pins, a 672‑BBGA surface-mount package (27×27 mm FBGA supplier footprint), a nominal core supply range of 1.425 V to 1.575 V, and a commercial operating temperature range of 0 °C to 85 °C.
Key Features
- Logic Array The device provides 10,570 logic elements suitable for scalable digital designs and protocol implementation.
- Embedded Memory Approximately 0.92 Mbits of on-chip RAM for FIFOs, buffers, and packet storage.
- High-Speed Serial Transceiver Technology (family-level) Stratix GX family transceivers include clock data recovery (CDR) and embedded SERDES supporting data rates up to 3.1875 Gbps and common high-speed serial protocols.
- Broad I/O Capability 362 I/O pins with support for multiple single-ended and differential I/O standards as provided by the Stratix GX architecture.
- DSP and Clocking Resources Family features include dedicated DSP blocks and multiple PLLs for clock multiplication, phase shifting, and real-time reconfiguration to support high-performance signal processing and timing control.
- Package & Mounting 672-BBGA (supplier package: 672-FBGA, 27×27 mm) in a surface-mount footprint suitable for compact board layouts.
- Power & Voltage Core supply specified from 1.425 V to 1.575 V, matching the Stratix GX 1.5‑V logic array operating range.
- Commercial Grade & RoHS Commercial temperature grade (0 °C to 85 °C) and RoHS‑compliant construction for standard commercial applications.
Typical Applications
- High‑speed backplane interfaces Use the Stratix GX family’s high-speed serial capabilities and dense logic fabric to implement backplane switching, aggregation, and protocol translation functions.
- Chip‑to‑chip interconnect Implement custom SERDES-based links and interface logic for board‑level or module-to-module high-speed data transfer.
- Communications protocol bridging Map between serial protocols and parallel logic or perform format conversion leveraging abundant logic elements and embedded RAM.
- Network and telecom equipment Deploy in commercial network equipment that requires programmable protocol adaptation and packet buffering within the stated temperature and supply ranges.
Unique Advantages
- Scalable programmable logic: 10,570 logic elements enable implementation of complex state machines, protocol stacks, and custom datapaths without external ASIC development.
- On-chip embedded memory: Approximately 0.92 Mbits of RAM supports FIFOs, packet buffering, and temporary storage, reducing the need for external memory in many designs.
- Family-level high-speed serial support: Stratix GX series transceivers (with CDR and SERDES) support up to 3.1875 Gbps data rates and common communications standards, simplifying high-speed link implementation.
- Flexible I/O and clocking: Extensive I/O count and the family’s PLL/DSP resources provide design flexibility for mixed-signal interfaces and high-performance timing architectures.
- Compact package: 672‑BBGA (27×27 mm) surface-mount package provides a high pin-count, compact footprint for space-constrained boards.
- Commercial readiness: Commercial temperature rating and RoHS compliance make the device appropriate for standard commercial electronic products and assemblies.
Why Choose EP1SGX10DF672C7N?
The EP1SGX10DF672C7N delivers a balanced combination of programmable logic density, embedded memory, and Stratix GX family high-speed serial capabilities in a compact 672‑BBGA package. It is well suited to commercial designs that require protocol bridging, high-speed links, and on-device buffering while operating within a 0 °C to 85 °C range and a 1.425 V–1.575 V core supply.
As part of the Stratix GX family, this FPGA offers architecture and transceiver features intended for communication-focused and high-throughput applications, providing a path for scalable implementations and integration within existing design flows.
Request a quote or submit a procurement inquiry to check availability and lead times for EP1SGX10DF672C7N.

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