XCV200-5BG352C
| Part Description |
Virtex® Field Programmable Gate Array (FPGA) IC 260 57344 5292 352-LBGA Exposed Pad, Metal |
|---|---|
| Quantity | 808 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | AMD |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 352-MBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 352-LBGA Exposed Pad, Metal | Number of I/O | 260 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1176 | Number of Logic Elements/Cells | 5292 | ||
| Number of Gates | 236666 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 57344 |
Overview of XCV200-5BG352C – Virtex® FPGA, 352-LBGA Exposed Pad (2.5 V)
The XCV200-5BG352C is a Virtex® Field Programmable Gate Array (FPGA) supplied in a 352‑LBGA exposed pad metal package. It provides a balance of programmable logic, embedded memory and I/O capacity for commercial embedded and system designs.
Built on the Virtex family architecture, this device delivers reprogrammable SRAM-based logic, multi-standard I/O support and on-chip memory suitable for applications such as PCI and Compact PCI systems, high-performance logic integration, and reconfigurable prototypes.
Key Features
- Programmable Logic 5,292 logic elements for implementing custom digital logic and control functions.
- On-chip Memory 57,344 bits of embedded RAM, selectable as various RAM widths or shift-register configurations for flexible data buffering and state storage.
- I/O Capacity 260 user I/O pins to support broad interfacing needs with external devices and buses.
- Clock and Timing Four dedicated delay-locked loops (DLLs) plus multiple global and local clock distribution nets for advanced clock control and low-skew routing.
- Multi-standard SelectIO Support for multiple high-performance interface standards and direct connectivity options to parallel memory devices.
- Performance and Standards Family-level support for system performance up to 200 MHz and 66‑MHz PCI compliance for compatible system integration.
- Configuration and Re-programmability SRAM-based in-system configuration with unlimited re-programmability and multiple programming modes.
- Package and Mounting Surface-mount 352‑LBGA exposed pad, metal package (supplier package 352‑MBGA 35×35) for compact board-level integration.
- Power and Temperature Core voltage supply range 2.375 V to 2.625 V; commercial operating temperature range 0 °C to 85 °C.
- Manufacturing and Reliability 0.22 µm 5‑layer metal process, 100% factory tested, IEEE 1149.1 boundary-scan and a die-temperature sensor diode included at the family level.
- Environmental RoHS compliant.
Typical Applications
- PCI and Compact PCI Systems Use the device’s PCI compliance and hot‑swap support at the family level for integration into PCI-based embedded platforms.
- Reconfigurable System Prototyping SRAM-based in-system programmability allows rapid iteration for hardware validation and prototype development.
- Custom Logic and Control Implement application-specific datapaths, control logic and glue functions using the device’s 5,292 logic elements and abundant I/O.
- High-performance Embedded Interfaces Leverage multi-standard SelectIO and the high I/O count to interface with external memories and peripherals.
Unique Advantages
- Reprogrammable Flexibility: SRAM-based configuration enables design updates in-system and supports multiple programming modes for deployment flexibility.
- High I/O Density: 260 I/O pins accommodate complex board-level connectivity without adding external interface logic.
- Integrated Memory Resources: 57,344 bits of on-chip RAM provide local buffering and state storage, reducing external memory dependence.
- Advanced Clocking: Dedicated DLLs and multiple clock nets simplify high-speed timing design and minimize skew across the fabric.
- Compact Package: 352‑LBGA exposed pad metal package (35×35) enables space-efficient surface-mount assembly for dense PCB layouts.
- Proven Manufacturing: 0.22 µm 5‑layer metal process and 100% factory testing provide predictable manufacturing quality.
Why Choose XCV200-5BG352C?
The XCV200-5BG352C is positioned for designers who need a reprogrammable, medium-density FPGA with substantial I/O and embedded RAM in a compact LBGA package. Its combination of 5,292 logic elements, 57,344 bits of on-chip memory and 260 I/O pins supports a wide range of commercial embedded and system-level designs where in-field reconfiguration and flexible interfacing are required.
Supported by the Virtex family development ecosystem, the device is suitable for teams seeking scalable programmable logic, board-level integration in a 352‑LBGA package, and the ability to iterate hardware functionality without changing silicon.
Request a quote or submit an inquiry to obtain pricing and availability for XCV200-5BG352C. Our team can provide lead-time and purchasing information to support your project timeline.

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