XCV300-6BG352C
| Part Description |
Virtex® Field Programmable Gate Array (FPGA) IC 260 65536 6912 352-LBGA Exposed Pad, Metal |
|---|---|
| Quantity | 938 Available (as of October 8, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | AMD |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 352-MBGA (35x35) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 352-LBGA Exposed Pad, Metal | Number of I/O | 260 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1536 | Number of Logic Elements/Cells | 6912 | ||
| Number of Gates | 322970 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 65536 |
Overview of XCV300-6BG352C – Virtex® FPGA, 6,912 Logic Elements, 65,536-bit RAM, 260 I/O, 352-LBGA
The XCV300-6BG352C is a Virtex® Field Programmable Gate Array (FPGA) in a 352-LBGA exposed-pad metal package designed for commercial applications. It provides a balance of high-density programmable logic, embedded memory, and a large I/O count for complex digital designs.
Built on the Virtex architecture, this SRAM-based FPGA supports in-system reconfiguration and is suited for performance-driven applications such as PCI-compliant systems, high-performance digital processing, and compact, reprogrammable logic implementations.
Key Features
- Logic Capacity — 6,912 logic elements and approximately 322,970 system gates provide substantial programmable logic for complex designs.
- Embedded Memory — 65,536 bits of on-chip RAM (approximately 64 Kbits) with LUTs that can be configured as various RAM types, dual-ported RAMs, or shift registers for flexible memory architectures.
- I/O and Interface Support — 260 general-purpose I/O pins and multi-standard SelectIO interfaces for broad connectivity and protocol flexibility. The device supports direct connections to a range of high-performance memories and interfaces.
- Clock Management — Four dedicated delay-locked loops (DLLs) plus four primary low-skew global clocks and 24 secondary local clock nets enable advanced clock control and low-skew distribution.
- Programmable Routing & Arithmetic Support — Dedicated carry logic, multiplier support, cascade chains for wide-input functions, and abundant registers/latches for high-speed arithmetic and control paths.
- Configuration & Test — SRAM-based in-system configuration with multiple programming modes, IEEE 1149.1 boundary-scan logic for testability, and 100% factory-tested devices.
- Process & Reliability — Manufactured in a 0.22 μm, 5-layer metal CMOS process; includes a die-temperature sensor diode for on-die thermal monitoring.
- Package & Supply — Surface-mount 352-LBGA exposed pad metal package (supplier package: 352-MBGA 35×35). Recommended supply voltage: 2.375 V to 2.625 V. Operating temperature: 0 °C to 85 °C (commercial grade). RoHS compliant.
Typical Applications
- PCI and Compact PCI Systems — PCI-compliant operation (66 MHz) and hot‑swappable support for Compact PCI make this device suitable for slot-based system modules and backplane designs.
- High-Performance Digital Processing — With up to 200 MHz system performance indicated for the Virtex family and dedicated arithmetic resources, the device is appropriate for demanding digital signal and control tasks.
- In-System Reprogrammable Logic — SRAM-based configuration enables field updates, prototyping, and iterative development workflows where reprogramming and design evolution are required.
- Interface Bridging and Protocol Conversion — High I/O count and multi-standard SelectIO capability support protocol bridging, bus interfacing, and custom peripheral integration.
Unique Advantages
- High-density programmable fabric: 6,912 logic elements and ~322,970 gates provide the capacity to integrate complex functions that reduce external components.
- Flexible embedded memory: 65,536 bits of on-chip RAM with configurable LUT-based RAM and dual-ported options lets designers tailor memory structures to algorithm needs.
- Extensive I/O connectivity: 260 I/O pins and multi-standard interface support enable direct interfacing to a wide range of peripherals and external memories.
- Advanced clocking resources: Four DLLs and a hierarchical clock distribution enable precise timing control across large designs.
- In-system configurability and test: SRAM-based configuration modes and IEEE 1149.1 boundary-scan support simplify development, updates, and manufacturing test.
- Commercial-grade thermal and power specs: Surface-mount 352-LBGA package with supply 2.375–2.625 V and operating range 0 °C to 85 °C aligns with standard commercial electronics environments.
Why Choose XCV300-6BG352C?
The XCV300-6BG352C delivers a balanced combination of logic capacity, embedded memory, and I/O density in a compact 352-LBGA package, making it suitable for designers who require reprogrammable, high-performance logic in commercial applications. As part of the Virtex family, it benefits from architecture features such as dedicated arithmetic resources, robust clock management, and a hierarchical routing fabric.
Supported by established FPGA development systems, this device is a practical choice for teams focused on reducing board-level complexity, accelerating prototyping cycles, and maintaining the flexibility to iterate designs in-system.
Request a quote or submit an inquiry for the XCV300-6BG352C to get pricing and availability details tailored to your project needs.

Date Founded: 1969
Headquarters: Santa Clara, California, USA
Employees: 25,000+
Revenue: $22.68 Billion
Certifications and Memberships: ISO9001:2015, RoHS, REACH








