XCV400-6BG560C
| Part Description |
Virtex® Field Programmable Gate Array (FPGA) IC 404 81920 10800 560-LBGA Exposed Pad, Metal |
|---|---|
| Quantity | 706 Available (as of October 7, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | AMD |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | Contact Us |
| Datasheet |
Specifications & Environmental
| Device Package | 560-MBGA (42.5x42.5) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 560-LBGA Exposed Pad, Metal | Number of I/O | 404 | Voltage | 2.375 V - 2.625 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 2400 | Number of Logic Elements/Cells | 10800 | ||
| Number of Gates | 468252 | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 81920 |
Overview of XCV400-6BG560C – Virtex® FPGA IC, 10,800 logic elements · 404 I/O · 560-LBGA
The XCV400-6BG560C is an AMD Virtex® SRAM-based field programmable gate array (FPGA) designed for high-density, reprogrammable logic implementations. It provides 10,800 logic elements, approximately 81,920 bits of on-chip RAM, and 404 user I/Os, making it suitable for designs that require substantial logic capacity, flexible I/O, and embedded memory.
This commercial-grade device is delivered in a 560-pin metal BGA with an exposed pad and supports a core supply range of 2.375 V to 2.625 V and an operating temperature range of 0 °C to 85 °C. It is RoHS compliant and 100% factory tested per the provided product specification.
Key Features
- Logic Capacity 10,800 logic elements and approximately 468,252 system gates to support complex, high-density logic designs.
- Embedded Memory Approximately 81,920 bits of on-chip RAM for buffering, temporary storage, and memory-mapped logic functions.
- I/O and Interfaces 404 user I/Os provide extensive external connectivity for custom interfaces and parallel/serial peripherals.
- Clock and Timing On-chip clock-management with four dedicated delay-locked loops (DLLs), four primary low-skew global clock distribution nets, and 24 secondary local clock nets for advanced clock control and low-skew distribution.
- Arithmetic and Logic Resources Dedicated carry logic, multiplier support, cascade chains for wide-input functions, and abundant registers with clock enable and synchronous/asynchronous set and reset.
- Configuration and Reprogrammability SRAM-based in-system configuration with unlimited re-programmability and multiple programming modes (as provided in the Virtex family documentation).
- Package and Mounting 560-LBGA metal package (supplier device package: 560-MBGA, 42.5 × 42.5 mm) with exposed pad; surface-mount mounting type.
- Power and Environmental Core supply voltage range of 2.375 V to 2.625 V; commercial operating temperature range 0 °C to 85 °C; RoHS compliant.
- Test and Diagnostics 100% factory tested with built-in IEEE 1149.1 boundary-scan logic and an on-die temperature sensor diode for system diagnostics.
Typical Applications
- Prototyping and Development Reprogrammable logic resources and abundant I/O make the device suitable for hardware prototyping and iterative design validation.
- Custom I/O Interfaces High I/O count supports bespoke parallel and serial interfaces and protocol bridging in embedded systems.
- High-density Logic Implementations Large logic capacity and embedded RAM enable consolidation of complex logic functions and data-paths into a single device.
- Clock-intensive Designs Integrated DLLs and multi-net clock distribution support applications that require precise clock control and low-skew timing across logic domains.
Unique Advantages
- Significant Logic Density: 10,800 logic elements and roughly 468k system gates provide room to implement complex algorithms and wide datapaths without partitioning across multiple devices.
- Generous I/O Count: 404 user I/Os reduce the need for external multiplexing and simplify board-level routing for multi-channel designs.
- Integrated Clock Management: Four DLLs and a hierarchical clock network simplify generation, distribution, and control of multiple clock domains on-chip.
- On-chip Memory Resources: Approximately 81,920 bits of embedded RAM support local buffering and small memory structures without external RAM components.
- Compact, Robust Package: 560-pin metal LBGA with exposed pad provides high pin count in a compact surface-mount form factor suitable for dense PCB layouts.
- Proven Manufacturing: Fabricated on a 0.22 μm, five-layer-metal process and 100% factory tested for consistent device quality.
Why Choose XCV400-6BG560C?
The XCV400-6BG560C delivers a balanced combination of logic capacity, I/O density, and embedded memory in a surface-mount 560-LBGA package. Its on-chip clock-management resources and dedicated arithmetic support simplify implementation of timing-sensitive and compute-heavy logic, while SRAM-based reprogrammability enables iterative development and in-system updates.
This device is well suited to customers and designs that require high-density programmable logic, extensive external connectivity, and built-in timing resources, all within a commercial temperature grade and RoHS-compliant package backed by comprehensive family-level documentation.
Request a quote or submit your requirements to receive pricing and availability for the XCV400-6BG560C.

Date Founded: 1969
Headquarters: Santa Clara, California, USA
Employees: 25,000+
Revenue: $22.68 Billion
Certifications and Memberships: ISO9001:2015, RoHS, REACH








