EP20K400EFC672-2X
| Part Description |
APEX-20KE® Field Programmable Gate Array (FPGA) IC 488 212992 16640 672-BBGA |
|---|---|
| Quantity | 588 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Obsolete |
| Manufacturer Standard Lead Time | RFQ |
| Datasheet |
Specifications & Environmental
| Device Package | 672-FBGA (27x27) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 672-BBGA | Number of I/O | 488 | Voltage | 1.71 V - 1.89 V | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS non-compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 1664 | Number of Logic Elements/Cells | 16640 | ||
| Number of Gates | 1052000 | ECCN | 3A001A7A | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 212992 |
Overview of EP20K400EFC672-2X – APEX-20KE® Field Programmable Gate Array (FPGA) 672-BBGA
The EP20K400EFC672-2X is an APEX-20KE family Field Programmable Gate Array (FPGA) from Intel. It implements a MultiCore architecture that integrates lookup-table (LUT) logic, product-term logic, and embedded system blocks (ESBs) to support both register- and memory-intensive functions on a single device.
Designed for system-on-a-programmable-chip (SOPC) integration, this device targets applications that require a high count of logic elements, substantial on-chip memory, and flexible high-speed I/O in a commercial-temperature FPGA solution.
Key Features
- Core architecture MultiCore architecture with LUT-based logic and product-term logic optimized for register- and combinatorial-intensive functions.
- Logic resources Approximately 16,640 logic elements and a maximum of 1,052,000 system gates, enabling complex digital designs.
- Embedded memory Approximately 0.213 Mbits of on-chip RAM (212,992 total RAM bits) provided by embedded system blocks for FIFOs, dual-port RAM and CAM implementations.
- I/O and interfaces 488 user I/O pins with MultiVolt I/O support and advanced I/O standards capability, plus programmable output slew-rate and individual tri-state control.
- Clocking and timing Flexible clock management with up to four PLLs, a built-in low-skew clock tree, up to eight global clocks, and ClockBoost/ClockShift features for programmable phase, delay, multiplication and division.
- Memory and bus support Support for high-speed external memories including DDR SDRAM and ZBT SRAM, and PCI Local Bus compliance for 3.3 V operation at 33/66 MHz (32/64 bits) as described in the device family data.
- Power Low-power design targeted around a 1.71 V to 1.89 V internal supply voltage range for the device core.
- Package and thermal 672-ball BGA package (supplier package: 672-FBGA, 27 × 27 mm) with commercial operating temperature range of 0 °C to 85 °C.
- Standards and compliance RoHS-compliant device.
Typical Applications
- PCI-based systems Implement PCI Local Bus interfaces and peripheral controllers leveraging the device’s PCI support and flexible I/O.
- Memory interface and buffering Build DDR SDRAM or ZBT SRAM controllers, FIFOs and memory-mapped buffering using the device’s embedded system blocks and ample on-chip RAM.
- High-speed serial links and LVDS Implement high-bandwidth channel interfaces and differential signaling using the device’s advanced I/O capabilities.
- System integration / SOPC Consolidate multiple system functions into a single FPGA using the MultiCore architecture and abundant logic elements for custom system integration.
Unique Advantages
- Integrated MultiCore architecture: Combines LUT logic, product-term logic and embedded memory to implement both register- and memory-heavy functions on a single device.
- Substantial logic and gate capacity: Approximately 16,640 logic elements and over one million system gates support complex logic integration without immediate upscaling.
- Embedded memory for on-chip buffering: Approximately 0.213 Mbits of RAM implemented in ESBs enables efficient FIFO, dual-port RAM and CAM designs.
- Comprehensive clock management: Multiple PLLs, global clocks and programmable clock features simplify timing architectures and reduce external clocking complexity.
- Flexible I/O and protocol support: MultiVolt I/O and wide support for advanced I/O standards allow direct interfacing with a variety of external devices and memory technologies.
- Compact BGA packaging: 672-ball BGA (27 × 27 mm) provides a high-density mount option for space-conscious system boards.
Why Choose EP20K400EFC672-2X?
The EP20K400EFC672-2X places a balance of logic density, embedded memory and flexible I/O into a commercial-temperature FPGA package. Its MultiCore architecture and embedded system blocks make it well suited for designs that require on-chip memory structures, complex state machines, and tight integration of multiple system functions.
Engineers and procurement teams looking for a RoHS-compliant FPGA with substantial logic resources, configurable clocking, and support for high-speed memories and PCI interfaces will find this device appropriate for mid- to high-complexity digital systems where integration and predictable timing are priorities.
Request a quote or submit an inquiry to receive pricing and availability for the EP20K400EFC672-2X.

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