EP2AGX125EF29C5G
| Part Description |
Arria II GX Field Programmable Gate Array (FPGA) IC 372 8315904 118143 780-BBGA, FCBGA |
|---|---|
| Quantity | 154 Available (as of May 5, 2026) |
| Product Category | Field Programmable Gate Array (FPGA) |
|---|---|
| Manufacturer | Intel |
| Manufacturing Status | Active |
| Manufacturer Standard Lead Time | 26 Weeks |
| Datasheet |
Specifications & Environmental
| Device Package | 780-FBGA (29x29) | Grade | Commercial | Operating Temperature | 0°C – 85°C | ||
|---|---|---|---|---|---|---|---|
| Package / Case | 780-BBGA, FCBGA | Number of I/O | 372 | Voltage | 870 mV - 930 mV | ||
| Mounting Method | Surface Mount | RoHS Compliance | RoHS Compliant | REACH Compliance | REACH Unaffected | ||
| Moisture Sensitivity Level | 3 (168 Hours) | Number of LABs/CLBs | 4964 | Number of Logic Elements/Cells | 118143 | ||
| Number of Gates | N/A | ECCN | 3A991D | HTS Code | 8542.39.0001 | ||
| Qualification | N/A | Total RAM Bits | 8315904 |
Overview of EP2AGX125EF29C5G – Arria II GX FPGA, 780‑BBGA FCBGA
The EP2AGX125EF29C5G is an Arria II GX field-programmable gate array in a 780‑BBGA (29×29) FCBGA package designed for surface-mount assembly. It delivers a mid-to-high logic capacity FPGA with integrated memory and transceiver-capable architecture suitable for commercial applications requiring programmable logic, embedded memory, and multi‑Gbps serial interfaces.
Built on the Arria II device family architecture, this device targets use cases in communications, data acquisition, high-bandwidth interfaces, and DSP-accelerated processing where a combination of logic density, embedded RAM, and configurable high-speed I/O is required.
Key Features
- Core Architecture 40‑nm low‑power Arria II FPGA architecture with adaptive logic modules and an eight‑input fracturable LUT for efficient logic implementation.
- Logic Capacity Approximately 118,143 logic elements to support medium-to-large programmable logic designs.
- Embedded Memory Approximately 8.3 Mbits of on‑chip RAM for FIFOs, buffering, and local data storage.
- DSP and Arithmetic Blocks Dedicated DSP blocks (documented up to 550 MHz) with configurable multipliers (9×9, 12×12, 18×18, 36×36 and 18×36 modes) and hardcoded add/subtract/accumulate functions for signal processing tasks.
- High‑Speed Transceivers & Interfaces Arria II family transceiver capabilities include support up to 6.375 Gbps and common serial protocols (PCIe, Ethernet, SATA, etc.) for high‑bandwidth system I/O (family-level feature set referenced in the device handbook).
- I/O and Packaging 372 user I/Os in a 780‑BBGA surface‑mount package (29×29 mm supplier package), enabling extensive board-level connectivity.
- Power and Supply Low‑power device characteristics with a documented core supply voltage range of 0.870 V to 0.930 V.
- Commercial Grade and Environmental Commercial temperature grade with an operating range of 0 °C to 85 °C and RoHS compliance.
Typical Applications
- Networking & Telecom Implement protocol layers and high‑speed serial links for Ethernet, PCIe, and similar interfaces using the Arria II family transceiver and PHY features.
- High‑Speed Data Acquisition Use the DSP blocks and on‑chip RAM for front‑end processing, buffering, and real‑time data handling in instrumentation and measurement systems.
- Storage & Connectivity Support storage interfaces and controllers leveraging the device’s serial protocol support and programmable logic for custom I/O and protocol offload.
- Prototyping and Embedded Systems Provide programmable acceleration, glue logic, and custom peripherals in commercial embedded designs.
Unique Advantages
- Balanced Logic and Memory Resource Mix: ~118k logic elements paired with ~8.3 Mbits of embedded RAM gives designers room for both combinational logic and local storage without external memory for many functions.
- Dedicated DSP Capability: On‑device DSP blocks and configurable multipliers shorten development time for signal processing tasks and reduce the need for external accelerators.
- High‑Speed Serial Support (Family-Level): Arria II family transceiver features enable implementation of multi‑Gbps links and protocol interfaces, easing integration of high‑bandwidth I/O.
- Compact, Surface‑Mount Packaging: 780‑BBGA (29×29) FCBGA package provides high I/O density in a surface‑mount form factor suitable for space‑constrained commercial PCBs.
- Power‑Aware Operation: Low‑power 40‑nm design with a defined core voltage range (0.870–0.930 V) supports power‑sensitive applications and predictable supply design.
Why Choose EP2AGX125EF29C5G?
The EP2AGX125EF29C5G combines the Arria II GX family’s 40‑nm low‑power architecture with a substantial logic element count and meaningful embedded memory capacity, making it a practical choice for commercial applications that need programmable logic, on‑chip RAM, and DSP acceleration. Its surface‑mount 780‑BBGA package and 372 I/O pins provide flexible board integration for high‑connectivity designs.
This device suits engineering teams building commercial communications equipment, data acquisition systems, storage controllers, and embedded platforms that leverage the Arria II family feature set for multi‑Gbps serial interfaces and DSP workloads while maintaining predictable supply and thermal requirements within the 0 °C to 85 °C operating range.
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